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Gate-Controlled WSe 2 Transistors Using a Buried Triple-Gate Structure

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ABSTRACT

In the present paper, we show tungsten diselenide (WSe2) devices that can be tuned to operate as n-type and p-type field-effect transistors (FETs) as well as band-to-band tunnel transistors on the same flake. Source, channel, and drain areas of the WSe2 flake are adjusted, using buried triple-gate substrates with three independently controllable gates. The device characteristics found in the tunnel transistor configuration are determined by the particular geometry of the buried triple-gate structure, consistent with a simple estimation of the expected off-state behavior.

No MeSH data available.


Schematic band diagrams for electrostatically doped nFET, pFET, and TFET devices. a Illustration in the case of zero gate voltage in source, drain, and gate area. b Positive side-gate voltages create n-type regions in source and drain, c a positive side-gate voltage in source and a negative side-gate voltage in drain yield a tunnel FET device. d In the case of negative side-gate voltages, p-type source/drain electrodes are realized
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Fig3: Schematic band diagrams for electrostatically doped nFET, pFET, and TFET devices. a Illustration in the case of zero gate voltage in source, drain, and gate area. b Positive side-gate voltages create n-type regions in source and drain, c a positive side-gate voltage in source and a negative side-gate voltage in drain yield a tunnel FET device. d In the case of negative side-gate voltages, p-type source/drain electrodes are realized

Mentions: Figure 3 illustrates the operational principle of our devices: For the realization of an nFET (Fig. 3b), positive and equal voltage is applied to both side-gates (this means that VSSG = VDSG > 0. For simplicity, this will be called side-gate voltage VSG in the following) which lowers the bands in the regions controlled by the side-gates (SSG and DSG) and yields an n-n doping profile. Note that all given voltages are in reference to the ground potential at the source contact. The described electrostatic doping yields a thinning of the source and drain Schottky barriers (SB) for electron injection while suppressing hole injection at the same time. As a result, a unipolar device behavior is expected in contrast to the usually observed ambipolar behavior of WSe2 transistors. Applying positive voltage to the center gate, i.e., the actual gate of the device (denoted with VG in the following), yields a lowering of the bands in the gate-controlled region (G) and switches the device on. The described mechanism can be employed similarly to realize a pFET device (i.e., a p-p doping profile) by applying VSG < 0, VG < 0 (cf. Fig. 3d). Figure 4 displays transfer characteristics of a WSe2 with a thickness of dWSe2 = 3 nm determined by AFM. The source-drain bias (VDS) is constant at 1 V and the various curves presented are from different side-gate voltages. The n-doping (Fig. 4a) leads to an increase of the drain current up to an Ion/Ioff ratio of >3 × 105 at VSG = 4 V. As already mentioned above, a pFET device is realized for VSG < 0, VG < 0. In this case, we find an Ion/Ioff ratio of ~103 at VSG = −4 V (cf. Fig. 4b). The ~100× larger n-current in comparison to the p-current (as well as the larger leakage current on the pFET compared to the nFET) is attributed to the influence of the nickel contacts, which were shown to be slightly more n-type [7, 30]. The subthreshold swings are 180 mV/dec (nFET) and 240 mV/dec (pFET), respectively. Note, that the current for large positive (n-type device) and negative (p-type device) gate voltages VG saturates, and current flow is then limited by the injection through the source-side SB. Since the tunneling probability is a function of the barrier height (0.54 and 0.74 eV in the case of electron and hole injection, respectively) and effective mass (0.34 and 0.44 m0 for electrons and holes, respectively), a different modulation of the tunneling probability through the SB is obtained for the n-type and the p-type [30]. As a result, the side-gates have considerably less impact on the SB in the p-type device which is reflected in the drain current for abs(VSG) > 2 V that hardly changes anymore.Fig. 3


Gate-Controlled WSe 2 Transistors Using a Buried Triple-Gate Structure
Schematic band diagrams for electrostatically doped nFET, pFET, and TFET devices. a Illustration in the case of zero gate voltage in source, drain, and gate area. b Positive side-gate voltages create n-type regions in source and drain, c a positive side-gate voltage in source and a negative side-gate voltage in drain yield a tunnel FET device. d In the case of negative side-gate voltages, p-type source/drain electrodes are realized
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Fig3: Schematic band diagrams for electrostatically doped nFET, pFET, and TFET devices. a Illustration in the case of zero gate voltage in source, drain, and gate area. b Positive side-gate voltages create n-type regions in source and drain, c a positive side-gate voltage in source and a negative side-gate voltage in drain yield a tunnel FET device. d In the case of negative side-gate voltages, p-type source/drain electrodes are realized
Mentions: Figure 3 illustrates the operational principle of our devices: For the realization of an nFET (Fig. 3b), positive and equal voltage is applied to both side-gates (this means that VSSG = VDSG > 0. For simplicity, this will be called side-gate voltage VSG in the following) which lowers the bands in the regions controlled by the side-gates (SSG and DSG) and yields an n-n doping profile. Note that all given voltages are in reference to the ground potential at the source contact. The described electrostatic doping yields a thinning of the source and drain Schottky barriers (SB) for electron injection while suppressing hole injection at the same time. As a result, a unipolar device behavior is expected in contrast to the usually observed ambipolar behavior of WSe2 transistors. Applying positive voltage to the center gate, i.e., the actual gate of the device (denoted with VG in the following), yields a lowering of the bands in the gate-controlled region (G) and switches the device on. The described mechanism can be employed similarly to realize a pFET device (i.e., a p-p doping profile) by applying VSG < 0, VG < 0 (cf. Fig. 3d). Figure 4 displays transfer characteristics of a WSe2 with a thickness of dWSe2 = 3 nm determined by AFM. The source-drain bias (VDS) is constant at 1 V and the various curves presented are from different side-gate voltages. The n-doping (Fig. 4a) leads to an increase of the drain current up to an Ion/Ioff ratio of >3 × 105 at VSG = 4 V. As already mentioned above, a pFET device is realized for VSG < 0, VG < 0. In this case, we find an Ion/Ioff ratio of ~103 at VSG = −4 V (cf. Fig. 4b). The ~100× larger n-current in comparison to the p-current (as well as the larger leakage current on the pFET compared to the nFET) is attributed to the influence of the nickel contacts, which were shown to be slightly more n-type [7, 30]. The subthreshold swings are 180 mV/dec (nFET) and 240 mV/dec (pFET), respectively. Note, that the current for large positive (n-type device) and negative (p-type device) gate voltages VG saturates, and current flow is then limited by the injection through the source-side SB. Since the tunneling probability is a function of the barrier height (0.54 and 0.74 eV in the case of electron and hole injection, respectively) and effective mass (0.34 and 0.44 m0 for electrons and holes, respectively), a different modulation of the tunneling probability through the SB is obtained for the n-type and the p-type [30]. As a result, the side-gates have considerably less impact on the SB in the p-type device which is reflected in the drain current for abs(VSG) > 2 V that hardly changes anymore.Fig. 3

View Article: PubMed Central - PubMed

ABSTRACT

In the present paper, we show tungsten diselenide (WSe2) devices that can be tuned to operate as n-type and p-type field-effect transistors (FETs) as well as band-to-band tunnel transistors on the same flake. Source, channel, and drain areas of the WSe2 flake are adjusted, using buried triple-gate substrates with three independently controllable gates. The device characteristics found in the tunnel transistor configuration are determined by the particular geometry of the buried triple-gate structure, consistent with a simple estimation of the expected off-state behavior.

No MeSH data available.