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Efficient BinDCT hardware architecture exploration and implementation on FPGA

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ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

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Proposed implementation (PI) performances.
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f0035: Proposed implementation (PI) performances.

Mentions: In addition, the static (Qp) and dynamic power (Dp) consumptions are estimated using the Xilinx XPower Analyzer. The following results are obtained: Qp = 3.532 mW and Dp = 0.107 mW. These consumption values represent lower values than those presented in the literature [7], [8], [23]. Fig. 7 summarizes the performances of the proposed implementation compared to the existing implementations of DCT approximations. The obtained performances show that the proposed implementation can be a good candidate for highly constrained images and video processing applications. It allows meeting the real time constraints of the most recent high resolution video formats, while presenting high hardware efficiency.


Efficient BinDCT hardware architecture exploration and implementation on FPGA
Proposed implementation (PI) performances.
© Copyright Policy - CC BY-NC-ND
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC5037209&req=5

f0035: Proposed implementation (PI) performances.
Mentions: In addition, the static (Qp) and dynamic power (Dp) consumptions are estimated using the Xilinx XPower Analyzer. The following results are obtained: Qp = 3.532 mW and Dp = 0.107 mW. These consumption values represent lower values than those presented in the literature [7], [8], [23]. Fig. 7 summarizes the performances of the proposed implementation compared to the existing implementations of DCT approximations. The obtained performances show that the proposed implementation can be a good candidate for highly constrained images and video processing applications. It allows meeting the real time constraints of the most recent high resolution video formats, while presenting high hardware efficiency.

View Article: PubMed Central - PubMed

ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

No MeSH data available.