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Efficient BinDCT hardware architecture exploration and implementation on FPGA

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ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

No MeSH data available.


2D-BinDCT architecture.
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f0030: 2D-BinDCT architecture.

Mentions: The implementation details of the 2D-BinDCT and the discussion of results are presented in this section, to wit the structure of the global architecture, the operations of the proposed architecture, the implementation results in terms of hardware resources and clock frequency, and the evaluation and comparison of performances. The suggested architecture is depicted in Fig. 6. It includes the following blocks: the “1st 1D-BinDCT input” block, the “1st 1 D-BinDCT” block, the “before SRAM” block, the “transpose SRAM” block, the “2nd 1D-BinDCT input” block, the “2nd 1D-BinDCT” block and the “2D-BinDCT output” block.


Efficient BinDCT hardware architecture exploration and implementation on FPGA
2D-BinDCT architecture.
© Copyright Policy - CC BY-NC-ND
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC5037209&req=5

f0030: 2D-BinDCT architecture.
Mentions: The implementation details of the 2D-BinDCT and the discussion of results are presented in this section, to wit the structure of the global architecture, the operations of the proposed architecture, the implementation results in terms of hardware resources and clock frequency, and the evaluation and comparison of performances. The suggested architecture is depicted in Fig. 6. It includes the following blocks: the “1st 1D-BinDCT input” block, the “1st 1 D-BinDCT” block, the “before SRAM” block, the “transpose SRAM” block, the “2nd 1D-BinDCT input” block, the “2nd 1D-BinDCT” block and the “2D-BinDCT output” block.

View Article: PubMed Central - PubMed

ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

No MeSH data available.