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Efficient BinDCT hardware architecture exploration and implementation on FPGA

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ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

No MeSH data available.


Architecture of the Input block.
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f0010: Architecture of the Input block.

Mentions: Each 1D-BinDCT block takes as an input eight line values, which have to be introduced simultaneously. In each of eight clock cycles, these 8 values are recovered from the serial input (Xin) and transmitted in parallel to the BinDCT stage 1 through the “input block”. Fig. 2 gives the hardware structure of the input block. It consists of 8 registers used to store the 8 line values (X0–X7) to be introduced to the 1D-BinDCT block and 8 shift registers for serial to parallel transformation of the input values.


Efficient BinDCT hardware architecture exploration and implementation on FPGA
Architecture of the Input block.
© Copyright Policy - CC BY-NC-ND
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC5037209&req=5

f0010: Architecture of the Input block.
Mentions: Each 1D-BinDCT block takes as an input eight line values, which have to be introduced simultaneously. In each of eight clock cycles, these 8 values are recovered from the serial input (Xin) and transmitted in parallel to the BinDCT stage 1 through the “input block”. Fig. 2 gives the hardware structure of the input block. It consists of 8 registers used to store the 8 line values (X0–X7) to be introduced to the 1D-BinDCT block and 8 shift registers for serial to parallel transformation of the input values.

View Article: PubMed Central - PubMed

ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

No MeSH data available.