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Efficient BinDCT hardware architecture exploration and implementation on FPGA

View Article: PubMed Central - PubMed

ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

No MeSH data available.


Diagram of the BinDCT.
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f0005: Diagram of the BinDCT.

Mentions: In our design, the lifting structure of the BinDCT family based on the Chen’s factorization (BinDCT type C) was utilized. Fig. 1 illustrates the flowchart of the forward BinDCT. Depending on the lifting parameters, several BinDCT configurations exist for Chen’s factorization: BinDCT-C1 to the BinDCT-C9 [4]. These configurations present a different number of arithmetic operations. BinDCT-C1 is the most accurate approximation among the other configurations, but it presents a higher computational cost. The BinDCT-C9 has the least accuracy and computation time. Each BinDCT configuration has different P and U value approximations, and consequently a different number of additions and shift operations.


Efficient BinDCT hardware architecture exploration and implementation on FPGA
Diagram of the BinDCT.
© Copyright Policy - CC BY-NC-ND
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC5037209&req=5

f0005: Diagram of the BinDCT.
Mentions: In our design, the lifting structure of the BinDCT family based on the Chen’s factorization (BinDCT type C) was utilized. Fig. 1 illustrates the flowchart of the forward BinDCT. Depending on the lifting parameters, several BinDCT configurations exist for Chen’s factorization: BinDCT-C1 to the BinDCT-C9 [4]. These configurations present a different number of arithmetic operations. BinDCT-C1 is the most accurate approximation among the other configurations, but it presents a higher computational cost. The BinDCT-C9 has the least accuracy and computation time. Each BinDCT configuration has different P and U value approximations, and consequently a different number of additions and shift operations.

View Article: PubMed Central - PubMed

ABSTRACT

This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

No MeSH data available.