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Fast Flexible Transistors with a Nanotrench Structure.

Seo JH, Ling T, Gong S, Zhou W, Ma AL, Guo LJ, Ma Z - Sci Rep (2016)

Bottom Line: On the other hand, recent advances in nanoimprinting lithography (NIL) may enable the fabrication of large-area nanoelectronics, especially flexible RF electronics with finely defined patterns, thereby significantly broadening RF applications.A unique 3-dimensional etched-trench-channel configuration was used to allow for TFT fabrication compatible with flexible substrates.Optimal device parameters were obtained through device simulation to understand the underlying device physics and to enhance device controllability.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706, USA.

ABSTRACT
The simplification of fabrication processes that can define very fine patterns for large-area flexible radio-frequency (RF) applications is very desirable because it is generally very challenging to realize submicron scale patterns on flexible substrates. Conventional nanoscale patterning methods, such as e-beam lithography, cannot be easily applied to such applications. On the other hand, recent advances in nanoimprinting lithography (NIL) may enable the fabrication of large-area nanoelectronics, especially flexible RF electronics with finely defined patterns, thereby significantly broadening RF applications. Here we report a generic strategy for fabricating high-performance flexible Si nanomembrane (NM)-based RF thin-film transistors (TFTs), capable of over 100 GHz operation in theory, with NIL patterned deep-submicron-scale channel lengths. A unique 3-dimensional etched-trench-channel configuration was used to allow for TFT fabrication compatible with flexible substrates. Optimal device parameters were obtained through device simulation to understand the underlying device physics and to enhance device controllability. Experimentally, a record-breaking 38 GHz maximum oscillation frequency fmax value has been successfully demonstrated from TFTs with a 2 μm gate length built with flexible Si NM on plastic substrates.

No MeSH data available.


Related in: MedlinePlus

Simulated current density near the channel region for different depths and widths of the trench.The total thickness of the Si NM (p− layer plus n+ layer) is 270 nm. The thickness of the n+ layer is 180 nm and that of the p− layer thickness is 90 nm. For all the scenarios simulated, the metal gate length (Lg) remains at 4 μm. (a) The trench width/channel length (Lch) is fixed at 100 nm. (a)(i) Simulated current density for a TFT with a 200 nm deep trench (20 nm of the trench depth extends into the p− layer: 70 nm p− layer remains as the active channel) revealing that the majority of the current flows through the trench surface and field-effect controllability is weak. (ii) At 220 nm deep (40 nm of the trench depth extends into the p− layer: 50 nm p− layer remains as the active channel), which is the middle value of the depth between the n+/p− interface and the top surface of Si NM, gate controllability is improved but a leakage current is still present through the trench. (iii) Simulated current density with the 250 nm deep trench (70 nm of the trench depth extends into the p− layer: 20 nm p− layer remains as the active channel) forms a very strong field-effected channel without a leakage current. (b) Dependence on the trench depth reduces as the width of the trench (Lch) becomes wider. The trench depth (D) is fixed at 200 nm. (i) The 100 nm wide and 200 nm deep trench shows a large leakage current near the trench surface. (ii) The 200 nm wide (Lch) trench significantly reduces the leakage current. (iii) The 500 nm wide (Lch) trench is completely free from the leakage current.
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f3: Simulated current density near the channel region for different depths and widths of the trench.The total thickness of the Si NM (p− layer plus n+ layer) is 270 nm. The thickness of the n+ layer is 180 nm and that of the p− layer thickness is 90 nm. For all the scenarios simulated, the metal gate length (Lg) remains at 4 μm. (a) The trench width/channel length (Lch) is fixed at 100 nm. (a)(i) Simulated current density for a TFT with a 200 nm deep trench (20 nm of the trench depth extends into the p− layer: 70 nm p− layer remains as the active channel) revealing that the majority of the current flows through the trench surface and field-effect controllability is weak. (ii) At 220 nm deep (40 nm of the trench depth extends into the p− layer: 50 nm p− layer remains as the active channel), which is the middle value of the depth between the n+/p− interface and the top surface of Si NM, gate controllability is improved but a leakage current is still present through the trench. (iii) Simulated current density with the 250 nm deep trench (70 nm of the trench depth extends into the p− layer: 20 nm p− layer remains as the active channel) forms a very strong field-effected channel without a leakage current. (b) Dependence on the trench depth reduces as the width of the trench (Lch) becomes wider. The trench depth (D) is fixed at 200 nm. (i) The 100 nm wide and 200 nm deep trench shows a large leakage current near the trench surface. (ii) The 200 nm wide (Lch) trench significantly reduces the leakage current. (iii) The 500 nm wide (Lch) trench is completely free from the leakage current.

Mentions: To address these challenges and enable large-scale fabrication of high-performance RF flexible electronics, we have designed and demonstrated high-performance flexible TFTs on a polyethylene terephthalate (PET) substrate (Fig. 1(a)). The flexible RF TFTs were fabricated on flexible Si NM employing a nano trench structure produced via nano-imprinting lithography (NIL) technology and were transfer printed onto a PET substrate. We employed Si NMs created from a silicon-on-insulator (SOI) wafer, instead of organic and amorphous semiconductor materials, in order to achieve high enough mobility for TFTs to operate in the RF regime. Si NMs have been widely used in versatile high performance flexible electronics and optoelectronics applications891011121314151617, because they not only have good flexibility and durability17, similar to other organic materials, but also have superior charge carrier mobility and saturation velocity8. One key feature of this novel TFT device structure is the nano trench formed in the Si NM via NIL, which is used to define a very small effective channel (as narrow as 100 nm)1819. Unlike the previous selective doping approach where the smallest feature size is limited by doping process control9101112, the physical feature size of NIL sets the limit and it is completely independent of the doping conditions for the source and drain regions. Furthermore, the effective channel length (Lch) is not affected by the actual length of the gate electrode (Lg). Namely, unlike the conventional methods, a deep submicron effective channel can be formed without the need of forming a nanoscale gate electrode. In this work, a longer gate-length electrode was deliberately used for easing and for reducing the cost of lithography. Such a structural advantage also offers a unique current path along with the trench (as marked in red in Fig. 1(a3)), which circumvents several physical issues when the effective channel length is reduced to the nanoscale, such as the short channel effect.


Fast Flexible Transistors with a Nanotrench Structure.

Seo JH, Ling T, Gong S, Zhou W, Ma AL, Guo LJ, Ma Z - Sci Rep (2016)

Simulated current density near the channel region for different depths and widths of the trench.The total thickness of the Si NM (p− layer plus n+ layer) is 270 nm. The thickness of the n+ layer is 180 nm and that of the p− layer thickness is 90 nm. For all the scenarios simulated, the metal gate length (Lg) remains at 4 μm. (a) The trench width/channel length (Lch) is fixed at 100 nm. (a)(i) Simulated current density for a TFT with a 200 nm deep trench (20 nm of the trench depth extends into the p− layer: 70 nm p− layer remains as the active channel) revealing that the majority of the current flows through the trench surface and field-effect controllability is weak. (ii) At 220 nm deep (40 nm of the trench depth extends into the p− layer: 50 nm p− layer remains as the active channel), which is the middle value of the depth between the n+/p− interface and the top surface of Si NM, gate controllability is improved but a leakage current is still present through the trench. (iii) Simulated current density with the 250 nm deep trench (70 nm of the trench depth extends into the p− layer: 20 nm p− layer remains as the active channel) forms a very strong field-effected channel without a leakage current. (b) Dependence on the trench depth reduces as the width of the trench (Lch) becomes wider. The trench depth (D) is fixed at 200 nm. (i) The 100 nm wide and 200 nm deep trench shows a large leakage current near the trench surface. (ii) The 200 nm wide (Lch) trench significantly reduces the leakage current. (iii) The 500 nm wide (Lch) trench is completely free from the leakage current.
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Related In: Results  -  Collection

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f3: Simulated current density near the channel region for different depths and widths of the trench.The total thickness of the Si NM (p− layer plus n+ layer) is 270 nm. The thickness of the n+ layer is 180 nm and that of the p− layer thickness is 90 nm. For all the scenarios simulated, the metal gate length (Lg) remains at 4 μm. (a) The trench width/channel length (Lch) is fixed at 100 nm. (a)(i) Simulated current density for a TFT with a 200 nm deep trench (20 nm of the trench depth extends into the p− layer: 70 nm p− layer remains as the active channel) revealing that the majority of the current flows through the trench surface and field-effect controllability is weak. (ii) At 220 nm deep (40 nm of the trench depth extends into the p− layer: 50 nm p− layer remains as the active channel), which is the middle value of the depth between the n+/p− interface and the top surface of Si NM, gate controllability is improved but a leakage current is still present through the trench. (iii) Simulated current density with the 250 nm deep trench (70 nm of the trench depth extends into the p− layer: 20 nm p− layer remains as the active channel) forms a very strong field-effected channel without a leakage current. (b) Dependence on the trench depth reduces as the width of the trench (Lch) becomes wider. The trench depth (D) is fixed at 200 nm. (i) The 100 nm wide and 200 nm deep trench shows a large leakage current near the trench surface. (ii) The 200 nm wide (Lch) trench significantly reduces the leakage current. (iii) The 500 nm wide (Lch) trench is completely free from the leakage current.
Mentions: To address these challenges and enable large-scale fabrication of high-performance RF flexible electronics, we have designed and demonstrated high-performance flexible TFTs on a polyethylene terephthalate (PET) substrate (Fig. 1(a)). The flexible RF TFTs were fabricated on flexible Si NM employing a nano trench structure produced via nano-imprinting lithography (NIL) technology and were transfer printed onto a PET substrate. We employed Si NMs created from a silicon-on-insulator (SOI) wafer, instead of organic and amorphous semiconductor materials, in order to achieve high enough mobility for TFTs to operate in the RF regime. Si NMs have been widely used in versatile high performance flexible electronics and optoelectronics applications891011121314151617, because they not only have good flexibility and durability17, similar to other organic materials, but also have superior charge carrier mobility and saturation velocity8. One key feature of this novel TFT device structure is the nano trench formed in the Si NM via NIL, which is used to define a very small effective channel (as narrow as 100 nm)1819. Unlike the previous selective doping approach where the smallest feature size is limited by doping process control9101112, the physical feature size of NIL sets the limit and it is completely independent of the doping conditions for the source and drain regions. Furthermore, the effective channel length (Lch) is not affected by the actual length of the gate electrode (Lg). Namely, unlike the conventional methods, a deep submicron effective channel can be formed without the need of forming a nanoscale gate electrode. In this work, a longer gate-length electrode was deliberately used for easing and for reducing the cost of lithography. Such a structural advantage also offers a unique current path along with the trench (as marked in red in Fig. 1(a3)), which circumvents several physical issues when the effective channel length is reduced to the nanoscale, such as the short channel effect.

Bottom Line: On the other hand, recent advances in nanoimprinting lithography (NIL) may enable the fabrication of large-area nanoelectronics, especially flexible RF electronics with finely defined patterns, thereby significantly broadening RF applications.A unique 3-dimensional etched-trench-channel configuration was used to allow for TFT fabrication compatible with flexible substrates.Optimal device parameters were obtained through device simulation to understand the underlying device physics and to enhance device controllability.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706, USA.

ABSTRACT
The simplification of fabrication processes that can define very fine patterns for large-area flexible radio-frequency (RF) applications is very desirable because it is generally very challenging to realize submicron scale patterns on flexible substrates. Conventional nanoscale patterning methods, such as e-beam lithography, cannot be easily applied to such applications. On the other hand, recent advances in nanoimprinting lithography (NIL) may enable the fabrication of large-area nanoelectronics, especially flexible RF electronics with finely defined patterns, thereby significantly broadening RF applications. Here we report a generic strategy for fabricating high-performance flexible Si nanomembrane (NM)-based RF thin-film transistors (TFTs), capable of over 100 GHz operation in theory, with NIL patterned deep-submicron-scale channel lengths. A unique 3-dimensional etched-trench-channel configuration was used to allow for TFT fabrication compatible with flexible substrates. Optimal device parameters were obtained through device simulation to understand the underlying device physics and to enhance device controllability. Experimentally, a record-breaking 38 GHz maximum oscillation frequency fmax value has been successfully demonstrated from TFTs with a 2 μm gate length built with flexible Si NM on plastic substrates.

No MeSH data available.


Related in: MedlinePlus