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Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

Wang F, Gong Z, Hu X, Yang X, Yang H, Gong Q - Sci Rep (2016)

Bottom Line: Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms.The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides.Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained.

View Article: PubMed Central - PubMed

Affiliation: State Key Laboratory for Mesoscopic Physics &Department of Physics, Collaborative Innovation Center of Quantum Matter, Peking University, Beijing 100871, People's Republic of China.

ABSTRACT
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

No MeSH data available.


Related in: MedlinePlus

Characterization of the U-shaped plasmonic waveguide.(a) Schematic diagram of waveguide structure. (b) Dispersion relations. (c) Power density profile of guided mode excited by incident CW light at a wavelength of 1560 nm.
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f1: Characterization of the U-shaped plasmonic waveguide.(a) Schematic diagram of waveguide structure. (b) Dispersion relations. (c) Power density profile of guided mode excited by incident CW light at a wavelength of 1560 nm.

Mentions: The U-shaped plasmonic waveguide structure is shown schematically in Fig. 1(a). The U-shaped plasmonic waveguide consists of an infinitely-long air groove with width of 200 nm and depth of 100 nm etched in a 300-nm-thick gold film. The dispersion relations of the plasmonic waveguide were calculated by the finite element method (using the commercial software package COMSOL Multiphysics)14, and the calculated results are shown in Fig. 1(b). The refractive index of air was set to 1, and the wavelength-dependent complex refractive index of gold was obtained from ref. 15. The U-shaped plasmonic waveguide can offer wideband guided SPP modes, as confirmed by the calculations of Li et al.16. To further confirm the properties of these guided SPP modes, we calculated the power density profile of a guided mode excited by continuous wave (CW) incident light at a wavelength of 1560 nm by the finite element method, and the calculated results are shown in Fig. 1(c). The guided mode is mainly confined within the groove region but extends slightly into the adjacent air regions. The waveguide is not etched completely through the gold film, although the energy would be confined to a smaller extent for reasons that will be stated at the end of this section. The maximum intensity is located at the gold-air interface around the two vertexes on the upper side, which is consistent with the calculations of Li et al.16. In our experiment, we etched a coupling grating connected to an air groove using a triangular configuration at the input port of the U-shaped plasmonic waveguide for efficient excitation and collection of the required SPPs for an input logic signal of 1. The grating period, the air groove length, the air groove width, and the air groove depth of this input coupling grating were 1.12 μm, 3 μm, 560 nm, and 300 nm, respectively. The input coupling grating was etched through the gold film to realize effective conversion from the incident light in free space to the SPP modes. The lateral length and depth of the triangular air groove were 3 μm and 100 nm, respectively. We also etched a grating into the output port to couple the guided SPP modes into free space for measurement purposes. The grating period, the air groove length, the air groove width, and the air groove depth of this decoupling grating were 1.12 μm, 3 μm, 560 nm, and 100 nm, respectively. Neither the U-shaped plasmonic waveguide nor the decoupling grating were etched through the gold film, thus ensuring that only the required scattering light signal of the SPP mode in the output waveguide can be obtained from the decoupling grating.


Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

Wang F, Gong Z, Hu X, Yang X, Yang H, Gong Q - Sci Rep (2016)

Characterization of the U-shaped plasmonic waveguide.(a) Schematic diagram of waveguide structure. (b) Dispersion relations. (c) Power density profile of guided mode excited by incident CW light at a wavelength of 1560 nm.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4829911&req=5

f1: Characterization of the U-shaped plasmonic waveguide.(a) Schematic diagram of waveguide structure. (b) Dispersion relations. (c) Power density profile of guided mode excited by incident CW light at a wavelength of 1560 nm.
Mentions: The U-shaped plasmonic waveguide structure is shown schematically in Fig. 1(a). The U-shaped plasmonic waveguide consists of an infinitely-long air groove with width of 200 nm and depth of 100 nm etched in a 300-nm-thick gold film. The dispersion relations of the plasmonic waveguide were calculated by the finite element method (using the commercial software package COMSOL Multiphysics)14, and the calculated results are shown in Fig. 1(b). The refractive index of air was set to 1, and the wavelength-dependent complex refractive index of gold was obtained from ref. 15. The U-shaped plasmonic waveguide can offer wideband guided SPP modes, as confirmed by the calculations of Li et al.16. To further confirm the properties of these guided SPP modes, we calculated the power density profile of a guided mode excited by continuous wave (CW) incident light at a wavelength of 1560 nm by the finite element method, and the calculated results are shown in Fig. 1(c). The guided mode is mainly confined within the groove region but extends slightly into the adjacent air regions. The waveguide is not etched completely through the gold film, although the energy would be confined to a smaller extent for reasons that will be stated at the end of this section. The maximum intensity is located at the gold-air interface around the two vertexes on the upper side, which is consistent with the calculations of Li et al.16. In our experiment, we etched a coupling grating connected to an air groove using a triangular configuration at the input port of the U-shaped plasmonic waveguide for efficient excitation and collection of the required SPPs for an input logic signal of 1. The grating period, the air groove length, the air groove width, and the air groove depth of this input coupling grating were 1.12 μm, 3 μm, 560 nm, and 300 nm, respectively. The input coupling grating was etched through the gold film to realize effective conversion from the incident light in free space to the SPP modes. The lateral length and depth of the triangular air groove were 3 μm and 100 nm, respectively. We also etched a grating into the output port to couple the guided SPP modes into free space for measurement purposes. The grating period, the air groove length, the air groove width, and the air groove depth of this decoupling grating were 1.12 μm, 3 μm, 560 nm, and 100 nm, respectively. Neither the U-shaped plasmonic waveguide nor the decoupling grating were etched through the gold film, thus ensuring that only the required scattering light signal of the SPP mode in the output waveguide can be obtained from the decoupling grating.

Bottom Line: Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms.The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides.Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained.

View Article: PubMed Central - PubMed

Affiliation: State Key Laboratory for Mesoscopic Physics &Department of Physics, Collaborative Innovation Center of Quantum Matter, Peking University, Beijing 100871, People's Republic of China.

ABSTRACT
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

No MeSH data available.


Related in: MedlinePlus