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High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics.

Shen LF, Yip S, Yang ZX, Fang M, Hung T, Pun EY, Ho JC - Sci Rep (2015)

Bottom Line: Here, we report the development of high-performance wrap-gated InGaAs NWFETs using conventional sputtered Al2O3 layers as gate dielectrics, instead of the typically employed atomic layer deposited counterparts.Utilizing this passivation, the wrap-gated device exhibits superior electrical performances: a high ION/IOFF ratio of ~ 2 × 10(6), an extremely low sub-threshold slope of 80 mV/decade and a peak field-effect electron mobility of ~ 1600 cm(2)/(Vs) at VDS = 0.1 V at room temperature, in which these values are even better than the ones of state-of-the-art NWFETs reported so far.By combining sputtering and pre-deposition chemical passivation to achieve high-quality gate dielectrics for wrap-gated NWFETs, the superior gate coupling and electrical performances have been achieved, confirming the effectiveness of our hybrid approach for future advanced electronic devices.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronic Engineering, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong.

ABSTRACT
Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using conventional sputtered Al2O3 layers as gate dielectrics, instead of the typically employed atomic layer deposited counterparts. Importantly, the surface chemical passivation of NW channels performed right before the dielectric deposition is found to significantly alleviate plasma induced defect traps on the NW channel. Utilizing this passivation, the wrap-gated device exhibits superior electrical performances: a high ION/IOFF ratio of ~ 2 × 10(6), an extremely low sub-threshold slope of 80 mV/decade and a peak field-effect electron mobility of ~ 1600 cm(2)/(Vs) at VDS = 0.1 V at room temperature, in which these values are even better than the ones of state-of-the-art NWFETs reported so far. By combining sputtering and pre-deposition chemical passivation to achieve high-quality gate dielectrics for wrap-gated NWFETs, the superior gate coupling and electrical performances have been achieved, confirming the effectiveness of our hybrid approach for future advanced electronic devices.

No MeSH data available.


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(a) Electron microscopy characterization of the as-grown InGaAs NWs; (b) High-resolution transmission electron microscope (HRTEM) image and the corresponding fast Fourier transform (FFT) of a representative NW; (c) EDS spectrum of the corresponding NW body.
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f1: (a) Electron microscopy characterization of the as-grown InGaAs NWs; (b) High-resolution transmission electron microscope (HRTEM) image and the corresponding fast Fourier transform (FFT) of a representative NW; (c) EDS spectrum of the corresponding NW body.

Mentions: The InGaAs NWs, synthesized by the two-step catalytic CVD method in this work, are dense, long (>10 μm), and straight with the smooth surface, as shown in the scanning electron microscope (SEM) image in Fig. 1a. In order to evaluate the crystallinity of the as-grown NWs, high-resolution transmission electron microscopy (HRTEM) are performed on a representative NW, as illustrated in Fig. 1b. Based on the plane spacing determination and the reciprocal lattice spots extracted by fast Fourier transform (FFT), the NW exhibits single-crystalline zinc-blende (ZB) structure with a dominant growth orientation in the <111> direction, and no significant amount of stacking faults or twin-plane polytypic defects are found in the samples. The spacing between the adjacent lattice planes are found to be 0.34 and 0.21 nm, which are in good agreement with the plane spacing of (111) and (022) equivalent planes in the In-rich thin-film counterparts, respectively35. Also, the NW stoichiometry can be assessed using the corresponding energy-dispersive X-ray spectroscopic (EDS) spectrum depicted in Fig. 1c. The In concentration x, being 0.58 in our ternary InxGa1−xAs NWs, is consistent with our previous work in controlling the NW composition by varying the precursor source powder ratio17.


High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics.

Shen LF, Yip S, Yang ZX, Fang M, Hung T, Pun EY, Ho JC - Sci Rep (2015)

(a) Electron microscopy characterization of the as-grown InGaAs NWs; (b) High-resolution transmission electron microscope (HRTEM) image and the corresponding fast Fourier transform (FFT) of a representative NW; (c) EDS spectrum of the corresponding NW body.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4660349&req=5

f1: (a) Electron microscopy characterization of the as-grown InGaAs NWs; (b) High-resolution transmission electron microscope (HRTEM) image and the corresponding fast Fourier transform (FFT) of a representative NW; (c) EDS spectrum of the corresponding NW body.
Mentions: The InGaAs NWs, synthesized by the two-step catalytic CVD method in this work, are dense, long (>10 μm), and straight with the smooth surface, as shown in the scanning electron microscope (SEM) image in Fig. 1a. In order to evaluate the crystallinity of the as-grown NWs, high-resolution transmission electron microscopy (HRTEM) are performed on a representative NW, as illustrated in Fig. 1b. Based on the plane spacing determination and the reciprocal lattice spots extracted by fast Fourier transform (FFT), the NW exhibits single-crystalline zinc-blende (ZB) structure with a dominant growth orientation in the <111> direction, and no significant amount of stacking faults or twin-plane polytypic defects are found in the samples. The spacing between the adjacent lattice planes are found to be 0.34 and 0.21 nm, which are in good agreement with the plane spacing of (111) and (022) equivalent planes in the In-rich thin-film counterparts, respectively35. Also, the NW stoichiometry can be assessed using the corresponding energy-dispersive X-ray spectroscopic (EDS) spectrum depicted in Fig. 1c. The In concentration x, being 0.58 in our ternary InxGa1−xAs NWs, is consistent with our previous work in controlling the NW composition by varying the precursor source powder ratio17.

Bottom Line: Here, we report the development of high-performance wrap-gated InGaAs NWFETs using conventional sputtered Al2O3 layers as gate dielectrics, instead of the typically employed atomic layer deposited counterparts.Utilizing this passivation, the wrap-gated device exhibits superior electrical performances: a high ION/IOFF ratio of ~ 2 × 10(6), an extremely low sub-threshold slope of 80 mV/decade and a peak field-effect electron mobility of ~ 1600 cm(2)/(Vs) at VDS = 0.1 V at room temperature, in which these values are even better than the ones of state-of-the-art NWFETs reported so far.By combining sputtering and pre-deposition chemical passivation to achieve high-quality gate dielectrics for wrap-gated NWFETs, the superior gate coupling and electrical performances have been achieved, confirming the effectiveness of our hybrid approach for future advanced electronic devices.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronic Engineering, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong.

ABSTRACT
Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using conventional sputtered Al2O3 layers as gate dielectrics, instead of the typically employed atomic layer deposited counterparts. Importantly, the surface chemical passivation of NW channels performed right before the dielectric deposition is found to significantly alleviate plasma induced defect traps on the NW channel. Utilizing this passivation, the wrap-gated device exhibits superior electrical performances: a high ION/IOFF ratio of ~ 2 × 10(6), an extremely low sub-threshold slope of 80 mV/decade and a peak field-effect electron mobility of ~ 1600 cm(2)/(Vs) at VDS = 0.1 V at room temperature, in which these values are even better than the ones of state-of-the-art NWFETs reported so far. By combining sputtering and pre-deposition chemical passivation to achieve high-quality gate dielectrics for wrap-gated NWFETs, the superior gate coupling and electrical performances have been achieved, confirming the effectiveness of our hybrid approach for future advanced electronic devices.

No MeSH data available.


Related in: MedlinePlus