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Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes.

Bai Y, Wu H, Wang K, Wu R, Song L, Li T, Wang J, Yu Z, Qian H - Sci Rep (2015)

Bottom Line: The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale.Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized.Furthermore, the discussion of high array density potential is presented.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Tsinghua University, Beijing, China, 100084.

ABSTRACT
There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

No MeSH data available.


3D RRAM array performance with Pt, graphene (GR) and CNT edge electrode.(a) The write access voltage of selected cell. (b) The read sense margin with a criterion of 80 mV.
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f7: 3D RRAM array performance with Pt, graphene (GR) and CNT edge electrode.(a) The write access voltage of selected cell. (b) The read sense margin with a criterion of 80 mV.

Mentions: Figure 7 show the performance of 3D RRAM with three types of edge electrodes at array level. The write access voltage versus array size in Fig. 7(a) shows the advantage of device with graphene and CNT edge electrodes. An obvious decline could be observed at 104 bits for device with Pt edge electrode. In contrast, for graphene and CNT edge electrode devices, the voltage degrade to 2 V when the array sizes increase to 108 bits and 1010 bits. The decrease of write access voltage mainly comes from the interconnect resistance. With the array size increase, the equivalent resistance of interconnect is comparable with RRAM cells, which causes the divided voltage on selected cell decrease. Therefore the 3D RRAM with Pt edge electrode has the limited array size due to small HRS/LRS resistances. For 3D RRAM cells with graphene and CNT edge electrodes, the HRS/LRS resistances are 1000X larger. This property offers much large array size without write access voltage degradation.


Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes.

Bai Y, Wu H, Wang K, Wu R, Song L, Li T, Wang J, Yu Z, Qian H - Sci Rep (2015)

3D RRAM array performance with Pt, graphene (GR) and CNT edge electrode.(a) The write access voltage of selected cell. (b) The read sense margin with a criterion of 80 mV.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4562297&req=5

f7: 3D RRAM array performance with Pt, graphene (GR) and CNT edge electrode.(a) The write access voltage of selected cell. (b) The read sense margin with a criterion of 80 mV.
Mentions: Figure 7 show the performance of 3D RRAM with three types of edge electrodes at array level. The write access voltage versus array size in Fig. 7(a) shows the advantage of device with graphene and CNT edge electrodes. An obvious decline could be observed at 104 bits for device with Pt edge electrode. In contrast, for graphene and CNT edge electrode devices, the voltage degrade to 2 V when the array sizes increase to 108 bits and 1010 bits. The decrease of write access voltage mainly comes from the interconnect resistance. With the array size increase, the equivalent resistance of interconnect is comparable with RRAM cells, which causes the divided voltage on selected cell decrease. Therefore the 3D RRAM with Pt edge electrode has the limited array size due to small HRS/LRS resistances. For 3D RRAM cells with graphene and CNT edge electrodes, the HRS/LRS resistances are 1000X larger. This property offers much large array size without write access voltage degradation.

Bottom Line: The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale.Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized.Furthermore, the discussion of high array density potential is presented.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Tsinghua University, Beijing, China, 100084.

ABSTRACT
There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

No MeSH data available.