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Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes.

Bai Y, Wu H, Wang K, Wu R, Song L, Li T, Wang J, Yu Z, Qian H - Sci Rep (2015)

Bottom Line: The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale.Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized.Furthermore, the discussion of high array density potential is presented.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Tsinghua University, Beijing, China, 100084.

ABSTRACT
There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

No MeSH data available.


(a) Schematic diagram of 3D Ta2O5-x/TaOy RRAM with CNT edge electrode; (b) TEM image of CNT with a diameter about 2.5nm; (c) The top view SEM image of the drilled hole after etching SiO2 layer without damaging the CNT electrode and (d) the metal contact Sc deposited on CNT; (e) The fabrication flow of the single 3D RRAM cell.
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f5: (a) Schematic diagram of 3D Ta2O5-x/TaOy RRAM with CNT edge electrode; (b) TEM image of CNT with a diameter about 2.5nm; (c) The top view SEM image of the drilled hole after etching SiO2 layer without damaging the CNT electrode and (d) the metal contact Sc deposited on CNT; (e) The fabrication flow of the single 3D RRAM cell.

Mentions: A novel approach of using CNT as the edge electrode and a self-integrated selector is proposed and devices are fabricated. Figure 5(a) shows the schematic view of the 3D Ta2O5-x/TaOy RRAM using CNT as the edge electrode. The effective area Seffective in this case is further reduced, which closes to the magnitude of CNT cross-section area. The fabrication process is similar to that of 3D RRAM with graphene edge electrode, as shown in Fig. 5(e). The CNT was synthesized on SiO2 substrate directly by CVD method26. Figure 5(b) shows the TEM image of semiconducting CNT which confirms the single wall property with a diameter of 2.5 nm. Since CNT is tiny, it is very challenge to get good electrical contact between TMO and CNT. CNT could be etched away during the hole etching process and leaves no electrical contact or bad electrical contact between TMO and CNT. Two-step etching process was specially designed to deliver good electrical contact between TMO and CNT: 1) etching the SiO2 insulator layer using HF chemistry which wouldn’t damage the CNT, as shown in Fig. 5(c); 2) etching the CNT using low power oxygen plasma in the drilled hole. Our experimental results showed that this two-step etching process could deliver repeatable and controllable holes without damaging CNT. In this 3D RRAM structure, metal Sc was chosen as the contact metal to CNT for signal output, as shown in Fig. 5(d). It is worth to point out that the architecture of CNT edge electrode based 3D RRAM array is different from the traditional 3D RRAM array (as shown in Fig. 1). To access each cell, the architecture in Figure S1 of supplemental material should be adopted which is suitable for other nanowire materials.


Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes.

Bai Y, Wu H, Wang K, Wu R, Song L, Li T, Wang J, Yu Z, Qian H - Sci Rep (2015)

(a) Schematic diagram of 3D Ta2O5-x/TaOy RRAM with CNT edge electrode; (b) TEM image of CNT with a diameter about 2.5nm; (c) The top view SEM image of the drilled hole after etching SiO2 layer without damaging the CNT electrode and (d) the metal contact Sc deposited on CNT; (e) The fabrication flow of the single 3D RRAM cell.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
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getmorefigures.php?uid=PMC4562297&req=5

f5: (a) Schematic diagram of 3D Ta2O5-x/TaOy RRAM with CNT edge electrode; (b) TEM image of CNT with a diameter about 2.5nm; (c) The top view SEM image of the drilled hole after etching SiO2 layer without damaging the CNT electrode and (d) the metal contact Sc deposited on CNT; (e) The fabrication flow of the single 3D RRAM cell.
Mentions: A novel approach of using CNT as the edge electrode and a self-integrated selector is proposed and devices are fabricated. Figure 5(a) shows the schematic view of the 3D Ta2O5-x/TaOy RRAM using CNT as the edge electrode. The effective area Seffective in this case is further reduced, which closes to the magnitude of CNT cross-section area. The fabrication process is similar to that of 3D RRAM with graphene edge electrode, as shown in Fig. 5(e). The CNT was synthesized on SiO2 substrate directly by CVD method26. Figure 5(b) shows the TEM image of semiconducting CNT which confirms the single wall property with a diameter of 2.5 nm. Since CNT is tiny, it is very challenge to get good electrical contact between TMO and CNT. CNT could be etched away during the hole etching process and leaves no electrical contact or bad electrical contact between TMO and CNT. Two-step etching process was specially designed to deliver good electrical contact between TMO and CNT: 1) etching the SiO2 insulator layer using HF chemistry which wouldn’t damage the CNT, as shown in Fig. 5(c); 2) etching the CNT using low power oxygen plasma in the drilled hole. Our experimental results showed that this two-step etching process could deliver repeatable and controllable holes without damaging CNT. In this 3D RRAM structure, metal Sc was chosen as the contact metal to CNT for signal output, as shown in Fig. 5(d). It is worth to point out that the architecture of CNT edge electrode based 3D RRAM array is different from the traditional 3D RRAM array (as shown in Fig. 1). To access each cell, the architecture in Figure S1 of supplemental material should be adopted which is suitable for other nanowire materials.

Bottom Line: The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale.Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized.Furthermore, the discussion of high array density potential is presented.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Tsinghua University, Beijing, China, 100084.

ABSTRACT
There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

No MeSH data available.