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Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes.

Bai Y, Wu H, Wang K, Wu R, Song L, Li T, Wang J, Yu Z, Qian H - Sci Rep (2015)

Bottom Line: The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale.Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized.Furthermore, the discussion of high array density potential is presented.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Tsinghua University, Beijing, China, 100084.

ABSTRACT
There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

No MeSH data available.


The typical schematic of 3D RRAM architecture.The sneak path currents exist in each vertical plane which dominates the maximum number of cells in the array. Therefore, the selector is a critical element to cut off the sneak path and achieve high density integration. The feature size scaling down of 3D RRAM can be divided into two parts: 1) the vertical direction decided by the thickness of metal plane; 2) the horizontal direction determined by the thickness of metal pillar, resistive switching layer and selector layer.
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f1: The typical schematic of 3D RRAM architecture.The sneak path currents exist in each vertical plane which dominates the maximum number of cells in the array. Therefore, the selector is a critical element to cut off the sneak path and achieve high density integration. The feature size scaling down of 3D RRAM can be divided into two parts: 1) the vertical direction decided by the thickness of metal plane; 2) the horizontal direction determined by the thickness of metal pillar, resistive switching layer and selector layer.

Mentions: The growing demands in high-density memories drive the rapid development of advanced memory technologies. As one of the most promising emerging non-volatile memory (NVM) devices, oxide-based resistive switching memory (RRAM) has attracted significant interests due to the super endurance, fast switching speed, low power consumption and good CMOS compatibility1234567. On the other hand, current flash technology also found a way to overcome its scaling limit by adopting three dimensional (3D) structure to achieve high density89. The 3D RRAM approach, which combines the advantages of excellent electrical performances in RRAM cell and high density of 3D configuration, becomes a very attractive candidate for next generation high density NVM applications101112. Since various 3D RRAM structures have been proposed, in this article, the 3D RRAM structure specifically refers to a typical architecture which is shown in Fig. 1: the RRAM cell is consisted with vertical resistive switching layer on the side wall of the drilled hole, vertical metal pillar as one electrode, and the edge of metal plane as the other electrode. Figure 1 shows that, different from planar RRAM, the effective area, Seffective, of 3D RRAM cell could be calculated as:


Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes.

Bai Y, Wu H, Wang K, Wu R, Song L, Li T, Wang J, Yu Z, Qian H - Sci Rep (2015)

The typical schematic of 3D RRAM architecture.The sneak path currents exist in each vertical plane which dominates the maximum number of cells in the array. Therefore, the selector is a critical element to cut off the sneak path and achieve high density integration. The feature size scaling down of 3D RRAM can be divided into two parts: 1) the vertical direction decided by the thickness of metal plane; 2) the horizontal direction determined by the thickness of metal pillar, resistive switching layer and selector layer.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4562297&req=5

f1: The typical schematic of 3D RRAM architecture.The sneak path currents exist in each vertical plane which dominates the maximum number of cells in the array. Therefore, the selector is a critical element to cut off the sneak path and achieve high density integration. The feature size scaling down of 3D RRAM can be divided into two parts: 1) the vertical direction decided by the thickness of metal plane; 2) the horizontal direction determined by the thickness of metal pillar, resistive switching layer and selector layer.
Mentions: The growing demands in high-density memories drive the rapid development of advanced memory technologies. As one of the most promising emerging non-volatile memory (NVM) devices, oxide-based resistive switching memory (RRAM) has attracted significant interests due to the super endurance, fast switching speed, low power consumption and good CMOS compatibility1234567. On the other hand, current flash technology also found a way to overcome its scaling limit by adopting three dimensional (3D) structure to achieve high density89. The 3D RRAM approach, which combines the advantages of excellent electrical performances in RRAM cell and high density of 3D configuration, becomes a very attractive candidate for next generation high density NVM applications101112. Since various 3D RRAM structures have been proposed, in this article, the 3D RRAM structure specifically refers to a typical architecture which is shown in Fig. 1: the RRAM cell is consisted with vertical resistive switching layer on the side wall of the drilled hole, vertical metal pillar as one electrode, and the edge of metal plane as the other electrode. Figure 1 shows that, different from planar RRAM, the effective area, Seffective, of 3D RRAM cell could be calculated as:

Bottom Line: The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale.Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized.Furthermore, the discussion of high array density potential is presented.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Tsinghua University, Beijing, China, 100084.

ABSTRACT
There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

No MeSH data available.