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CMOS-Compatible Top-Down Fabrication of Periodic SiO2 Nanostructures using a Single Mask.

Meng L, Gao J, He X, Li J, Wei Y, Yan J - Nanoscale Res Lett (2015)

Bottom Line: It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls.Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable.It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, People's Republic of China, menglingkuan@ime.ac.cn.

ABSTRACT
We propose a CMOS-compatible top-down fabrication technique of highly-ordered and periodic SiO2 nanostructures using a single amorphous silicon (α-Si) mask layer. The α-Si mask pattern is precisely transferred into the underlying SiO2 substrate material with a high fidelity by a novel top-down fabrication. It is the first time for α-Si film used as an etch mask to fabricate SiO2 nanostructures including nanoline, nanotrench, and nanohole arrays. It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls. This behavior may be attributed to the presence of high concentration of dangling bonds in α-Si mask surface. By controlling the process condition, it is possible to achieve a desired vertical etched profile with a controlled size. Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable. The obtained SiO2 pattern can be further used as a nanotemplate to produce periodic or more complex silicon nanostructures. Moreover, this novel top-down approach is a potentially universal method that is fully compatible with the currently existing Si-based CMOS technologies. It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

No MeSH data available.


SEM images of the fabrication of periodic silicon nanotrench arrays with 40 nm line width and 40-nm spacing. a Arrays of α-Si mask nanotrench are patterned by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. b SiO2 nanotrench arrays fabricated show a highly uniform and vertical etched profile. cTop view of (b) showing a highly smooth sidewalls
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Fig4: SEM images of the fabrication of periodic silicon nanotrench arrays with 40 nm line width and 40-nm spacing. a Arrays of α-Si mask nanotrench are patterned by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. b SiO2 nanotrench arrays fabricated show a highly uniform and vertical etched profile. cTop view of (b) showing a highly smooth sidewalls

Mentions: Figure 4 shows cross-sectional SEM images of a highly ordered and periodic SiO2 nanotrench arrays fabricated using a single α-Si mask with the same e-beam lithography condition as described in Fig. 2. As presented above, to create SiO2 nanotrench arrays, α-Si mask is firstly patterned by a mixture gas of Cl2/HBr/O2 in an ICP chamber, as shown in Fig. 4a. Note that here, it should be pointed out that the remaining resist film after α-Si mask patterning is very necessarily removed in order to avoid a not good influence on the fabrication of SiO2 nanotrench arrays. Otherwise, in this case, it will be very difficult to obtain smooth and desirable SiO2 features, and a severe patterning distortion is easily produced. The resist removal can be achieved by an O2 plasma ashing in combination with a wet cleaning process composed of a dip in dilute hydrofluoric acid (DHF) followed by sulfuric peroxide mixtures (SPM). Then, the periodic α-Si patterns formed by the resist are transferred into the underlying SiO2 film in the LAM Exelan Hpt etcher. Pattern transfer with a high fidelity into the underlying SiO2 film to create a high aspect ratio structure is always a challenge in nanometer scales. Here, an optimized process condition is developed to achieve a good pattern transfer using a fluorocarbon-based plasma chemistry including C4F6/CO/O2/Ar mixture gases. As shown in Fig. 4b, c, it is evident that the resulting nanotrench arrays retain highly ordered and periodic nanostructure with an opening width of around 35 nm. The cross-sectional view of nanotrench arrays demonstrates that all etched SiO2 trenches are highly uniform and smooth, showing an excellent uniformity and high reproducibility by simply using the α-Si mask. The etched depth of the SiO2 nanotrench can be easily controlled by processing time. Figure 4b, c shows that SiO2 nanotrench arrays fabricated have a width of 35 nm with a nearly vertical etched profile as well as fairly smooth sidewalls.Fig. 4


CMOS-Compatible Top-Down Fabrication of Periodic SiO2 Nanostructures using a Single Mask.

Meng L, Gao J, He X, Li J, Wei Y, Yan J - Nanoscale Res Lett (2015)

SEM images of the fabrication of periodic silicon nanotrench arrays with 40 nm line width and 40-nm spacing. a Arrays of α-Si mask nanotrench are patterned by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. b SiO2 nanotrench arrays fabricated show a highly uniform and vertical etched profile. cTop view of (b) showing a highly smooth sidewalls
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Fig4: SEM images of the fabrication of periodic silicon nanotrench arrays with 40 nm line width and 40-nm spacing. a Arrays of α-Si mask nanotrench are patterned by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. b SiO2 nanotrench arrays fabricated show a highly uniform and vertical etched profile. cTop view of (b) showing a highly smooth sidewalls
Mentions: Figure 4 shows cross-sectional SEM images of a highly ordered and periodic SiO2 nanotrench arrays fabricated using a single α-Si mask with the same e-beam lithography condition as described in Fig. 2. As presented above, to create SiO2 nanotrench arrays, α-Si mask is firstly patterned by a mixture gas of Cl2/HBr/O2 in an ICP chamber, as shown in Fig. 4a. Note that here, it should be pointed out that the remaining resist film after α-Si mask patterning is very necessarily removed in order to avoid a not good influence on the fabrication of SiO2 nanotrench arrays. Otherwise, in this case, it will be very difficult to obtain smooth and desirable SiO2 features, and a severe patterning distortion is easily produced. The resist removal can be achieved by an O2 plasma ashing in combination with a wet cleaning process composed of a dip in dilute hydrofluoric acid (DHF) followed by sulfuric peroxide mixtures (SPM). Then, the periodic α-Si patterns formed by the resist are transferred into the underlying SiO2 film in the LAM Exelan Hpt etcher. Pattern transfer with a high fidelity into the underlying SiO2 film to create a high aspect ratio structure is always a challenge in nanometer scales. Here, an optimized process condition is developed to achieve a good pattern transfer using a fluorocarbon-based plasma chemistry including C4F6/CO/O2/Ar mixture gases. As shown in Fig. 4b, c, it is evident that the resulting nanotrench arrays retain highly ordered and periodic nanostructure with an opening width of around 35 nm. The cross-sectional view of nanotrench arrays demonstrates that all etched SiO2 trenches are highly uniform and smooth, showing an excellent uniformity and high reproducibility by simply using the α-Si mask. The etched depth of the SiO2 nanotrench can be easily controlled by processing time. Figure 4b, c shows that SiO2 nanotrench arrays fabricated have a width of 35 nm with a nearly vertical etched profile as well as fairly smooth sidewalls.Fig. 4

Bottom Line: It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls.Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable.It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, People's Republic of China, menglingkuan@ime.ac.cn.

ABSTRACT
We propose a CMOS-compatible top-down fabrication technique of highly-ordered and periodic SiO2 nanostructures using a single amorphous silicon (α-Si) mask layer. The α-Si mask pattern is precisely transferred into the underlying SiO2 substrate material with a high fidelity by a novel top-down fabrication. It is the first time for α-Si film used as an etch mask to fabricate SiO2 nanostructures including nanoline, nanotrench, and nanohole arrays. It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls. This behavior may be attributed to the presence of high concentration of dangling bonds in α-Si mask surface. By controlling the process condition, it is possible to achieve a desired vertical etched profile with a controlled size. Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable. The obtained SiO2 pattern can be further used as a nanotemplate to produce periodic or more complex silicon nanostructures. Moreover, this novel top-down approach is a potentially universal method that is fully compatible with the currently existing Si-based CMOS technologies. It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

No MeSH data available.