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CMOS-Compatible Top-Down Fabrication of Periodic SiO2 Nanostructures using a Single Mask.

Meng L, Gao J, He X, Li J, Wei Y, Yan J - Nanoscale Res Lett (2015)

Bottom Line: It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls.Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable.It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, People's Republic of China, menglingkuan@ime.ac.cn.

ABSTRACT
We propose a CMOS-compatible top-down fabrication technique of highly-ordered and periodic SiO2 nanostructures using a single amorphous silicon (α-Si) mask layer. The α-Si mask pattern is precisely transferred into the underlying SiO2 substrate material with a high fidelity by a novel top-down fabrication. It is the first time for α-Si film used as an etch mask to fabricate SiO2 nanostructures including nanoline, nanotrench, and nanohole arrays. It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls. This behavior may be attributed to the presence of high concentration of dangling bonds in α-Si mask surface. By controlling the process condition, it is possible to achieve a desired vertical etched profile with a controlled size. Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable. The obtained SiO2 pattern can be further used as a nanotemplate to produce periodic or more complex silicon nanostructures. Moreover, this novel top-down approach is a potentially universal method that is fully compatible with the currently existing Si-based CMOS technologies. It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

No MeSH data available.


Related in: MedlinePlus

SEM images of the fabrication of periodic silicon nanoline arrays with 20 nm line width and 40-nm spacing. a Arrays of the resist nanoline with a width of 20 nm are patterned by e-beam lithography, and the bright area was the line. b Arrays of α-Si mask nanoline are fabricated by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. c The silicon nanoline arrays are successfully fabricated by a high fidelity pattern transfer from α-Si mask and SiO2 nanotemplate, demonstrating a nearly vertical etched profile as well as the smooth sidewalls
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Fig3: SEM images of the fabrication of periodic silicon nanoline arrays with 20 nm line width and 40-nm spacing. a Arrays of the resist nanoline with a width of 20 nm are patterned by e-beam lithography, and the bright area was the line. b Arrays of α-Si mask nanoline are fabricated by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. c The silicon nanoline arrays are successfully fabricated by a high fidelity pattern transfer from α-Si mask and SiO2 nanotemplate, demonstrating a nearly vertical etched profile as well as the smooth sidewalls

Mentions: Figure 3 demonstrates a typical fabrication applied in photonic devices or nanofluidic devices by silicon arrays. Due to resolution limit of e-beam resist, for the resist patterns with the line width of 20 nm, there are considerably numbers of burrs that can be found in the line edge. Here, we first fabricate the SiO2 nanotemplate using the same approach proposed above, and then it is precisely transferred into the underlying silicon substrate to produce periodic silicon nanoline arrays in halogen-based plasma chemistry by a mixture of Cl2 and HBr. As shown in Fig. 3c, it is observed that highly ordered and periodic silicon arrays with smooth sidewalls have been successfully achieved, having a line width of 20 nm, a period of 60 nm, as well as a fairly high aspect ratio structure of near 5:1 with almost vertical etched profiles. Higher aspect ratio silicon arrays can be easily achieved by increasing thickness of SiO2 film without the requirement of adding an extra process. It indicates that the ultimate limit of etched feature size is determined by the patterning ability of lithography technology rather than the approach itself proposed in this work.Fig. 3


CMOS-Compatible Top-Down Fabrication of Periodic SiO2 Nanostructures using a Single Mask.

Meng L, Gao J, He X, Li J, Wei Y, Yan J - Nanoscale Res Lett (2015)

SEM images of the fabrication of periodic silicon nanoline arrays with 20 nm line width and 40-nm spacing. a Arrays of the resist nanoline with a width of 20 nm are patterned by e-beam lithography, and the bright area was the line. b Arrays of α-Si mask nanoline are fabricated by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. c The silicon nanoline arrays are successfully fabricated by a high fidelity pattern transfer from α-Si mask and SiO2 nanotemplate, demonstrating a nearly vertical etched profile as well as the smooth sidewalls
© Copyright Policy - OpenAccess
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4549353&req=5

Fig3: SEM images of the fabrication of periodic silicon nanoline arrays with 20 nm line width and 40-nm spacing. a Arrays of the resist nanoline with a width of 20 nm are patterned by e-beam lithography, and the bright area was the line. b Arrays of α-Si mask nanoline are fabricated by a precise pattern transfer in ICP etcher by Cl2/HBr/O2 plasma chemistry. c The silicon nanoline arrays are successfully fabricated by a high fidelity pattern transfer from α-Si mask and SiO2 nanotemplate, demonstrating a nearly vertical etched profile as well as the smooth sidewalls
Mentions: Figure 3 demonstrates a typical fabrication applied in photonic devices or nanofluidic devices by silicon arrays. Due to resolution limit of e-beam resist, for the resist patterns with the line width of 20 nm, there are considerably numbers of burrs that can be found in the line edge. Here, we first fabricate the SiO2 nanotemplate using the same approach proposed above, and then it is precisely transferred into the underlying silicon substrate to produce periodic silicon nanoline arrays in halogen-based plasma chemistry by a mixture of Cl2 and HBr. As shown in Fig. 3c, it is observed that highly ordered and periodic silicon arrays with smooth sidewalls have been successfully achieved, having a line width of 20 nm, a period of 60 nm, as well as a fairly high aspect ratio structure of near 5:1 with almost vertical etched profiles. Higher aspect ratio silicon arrays can be easily achieved by increasing thickness of SiO2 film without the requirement of adding an extra process. It indicates that the ultimate limit of etched feature size is determined by the patterning ability of lithography technology rather than the approach itself proposed in this work.Fig. 3

Bottom Line: It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls.Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable.It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

View Article: PubMed Central - PubMed

Affiliation: Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, People's Republic of China, menglingkuan@ime.ac.cn.

ABSTRACT
We propose a CMOS-compatible top-down fabrication technique of highly-ordered and periodic SiO2 nanostructures using a single amorphous silicon (α-Si) mask layer. The α-Si mask pattern is precisely transferred into the underlying SiO2 substrate material with a high fidelity by a novel top-down fabrication. It is the first time for α-Si film used as an etch mask to fabricate SiO2 nanostructures including nanoline, nanotrench, and nanohole arrays. It is observed that the α-Si mask can significantly reduce the pattern edge roughness and achieve highly uniform and smooth sidewalls. This behavior may be attributed to the presence of high concentration of dangling bonds in α-Si mask surface. By controlling the process condition, it is possible to achieve a desired vertical etched profile with a controlled size. Our results demonstrate that SiO2 pattern as small as sub-20 nm may be achievable. The obtained SiO2 pattern can be further used as a nanotemplate to produce periodic or more complex silicon nanostructures. Moreover, this novel top-down approach is a potentially universal method that is fully compatible with the currently existing Si-based CMOS technologies. It offers a greater flexibility for the fabrication of various nanoscale devices in a simple and efficient way.

No MeSH data available.


Related in: MedlinePlus