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Logic circuits from zero forcing.

Burgarth D, Giovannetti V, Hogben L, Severini S, Young M - Nat Comput (2015)

Bottom Line: Finally, we show that zero forcing can be also used to implement reversible computation.The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity.It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

View Article: PubMed Central - PubMed

Affiliation: Department of Mathematics and Physics, Aberystwyth University, Aberystwyth, SY23 3BZ UK.

ABSTRACT

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

No MeSH data available.


The gate for the function OR
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Fig2: The gate for the function OR

Mentions: Claim 2 The gate OR is realized by the gadget with vertices and edges , where and are the input vertices. The output vertex is vertex . Vertex is initially colored black. See Fig. 2.Fig. 1


Logic circuits from zero forcing.

Burgarth D, Giovannetti V, Hogben L, Severini S, Young M - Nat Comput (2015)

The gate for the function OR
© Copyright Policy - OpenAccess
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4541710&req=5

Fig2: The gate for the function OR
Mentions: Claim 2 The gate OR is realized by the gadget with vertices and edges , where and are the input vertices. The output vertex is vertex . Vertex is initially colored black. See Fig. 2.Fig. 1

Bottom Line: Finally, we show that zero forcing can be also used to implement reversible computation.The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity.It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

View Article: PubMed Central - PubMed

Affiliation: Department of Mathematics and Physics, Aberystwyth University, Aberystwyth, SY23 3BZ UK.

ABSTRACT

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

No MeSH data available.