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Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.

Cheng YC, Chen HB, Su JJ, Shao CS, Wang CP, Chang CY, Wu YC - Nanoscale Res Lett (2014)

Bottom Line: Using a thin channel structure obtains excellent performance in the raised S/D structure.Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs.This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu, 30013, Taiwan, citygirl0831@hotmail.com.

ABSTRACT
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

No MeSH data available.


Simulation results at (a) G1 = 1 V, G2 = −4 V for mode 2 situation and (b) G1 = −4 V, G2 = 1 V for mode 1 situation.
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Fig9: Simulation results at (a) G1 = 1 V, G2 = −4 V for mode 2 situation and (b) G1 = −4 V, G2 = 1 V for mode 1 situation.

Mentions: Figure 5 shows the dual-gate structure with different operation modes. In mode 1, G1 is sweeping, G2 has an off-state bias condition, and Vd is applied at −0.3 V. In mode 2, G1 is sweeping, and G2 has an on-state bias condition. The reverse conditions for G1 and G2 occur in mode 3 and mode 4. Figure 6 shows the Id-Vg characteristics. The red line represents that G1 is floating and G2 is sweeping. The blue line represents that G1 connects G2 and they are sweeping simultaneously. The experimental data show a good match in the Id-Vg curves, which indicates that the series resistance between G1 and G2 is insignificant and does not degrade electrical performance. The inset in Figure 6 shows the scanning electron microscope (SEM) image of the dual-gate structure. The distance between the dual gate is 0.5 μm. Figure 7 depicts the Id-Vg curves for different operation modes. The electrical performances for mode 1 and mode 2 are similar to those for mode 3 and mode 4 at Vd = −0.3 V. Figure 7a,c shows that, when the G2 and G1 approaches off-state bias condition, the on current is clearly pinning and absolute Vth is increasing. Figure 7b,d shows that, when the G2 and G1 approaches on-state bias condition, the on current is increasing and the absoute Vth is decreasing. In Figure 8a, the Vth can be adjusted by the dual-gate structure applying different gate bias. In Figure 8b, the Vth sensitivity of G2 bias is approximately 1.23 V/V, and the experimental data show that the relationship is linear. The detailed results are discussed by 3D TCAD simulation in Figure 9. To obtain accurate numerical results for a nanometer-scale device, the device is simulated by solving 3D quantum-corrected equations using the commercial tool, Synopsys Sentaurus Device [14]. In quantum-corrected equations, a density gradient model is used in the simulation, as listed below [15, 16]:2


Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.

Cheng YC, Chen HB, Su JJ, Shao CS, Wang CP, Chang CY, Wu YC - Nanoscale Res Lett (2014)

Simulation results at (a) G1 = 1 V, G2 = −4 V for mode 2 situation and (b) G1 = −4 V, G2 = 1 V for mode 1 situation.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4493839&req=5

Fig9: Simulation results at (a) G1 = 1 V, G2 = −4 V for mode 2 situation and (b) G1 = −4 V, G2 = 1 V for mode 1 situation.
Mentions: Figure 5 shows the dual-gate structure with different operation modes. In mode 1, G1 is sweeping, G2 has an off-state bias condition, and Vd is applied at −0.3 V. In mode 2, G1 is sweeping, and G2 has an on-state bias condition. The reverse conditions for G1 and G2 occur in mode 3 and mode 4. Figure 6 shows the Id-Vg characteristics. The red line represents that G1 is floating and G2 is sweeping. The blue line represents that G1 connects G2 and they are sweeping simultaneously. The experimental data show a good match in the Id-Vg curves, which indicates that the series resistance between G1 and G2 is insignificant and does not degrade electrical performance. The inset in Figure 6 shows the scanning electron microscope (SEM) image of the dual-gate structure. The distance between the dual gate is 0.5 μm. Figure 7 depicts the Id-Vg curves for different operation modes. The electrical performances for mode 1 and mode 2 are similar to those for mode 3 and mode 4 at Vd = −0.3 V. Figure 7a,c shows that, when the G2 and G1 approaches off-state bias condition, the on current is clearly pinning and absolute Vth is increasing. Figure 7b,d shows that, when the G2 and G1 approaches on-state bias condition, the on current is increasing and the absoute Vth is decreasing. In Figure 8a, the Vth can be adjusted by the dual-gate structure applying different gate bias. In Figure 8b, the Vth sensitivity of G2 bias is approximately 1.23 V/V, and the experimental data show that the relationship is linear. The detailed results are discussed by 3D TCAD simulation in Figure 9. To obtain accurate numerical results for a nanometer-scale device, the device is simulated by solving 3D quantum-corrected equations using the commercial tool, Synopsys Sentaurus Device [14]. In quantum-corrected equations, a density gradient model is used in the simulation, as listed below [15, 16]:2

Bottom Line: Using a thin channel structure obtains excellent performance in the raised S/D structure.Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs.This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu, 30013, Taiwan, citygirl0831@hotmail.com.

ABSTRACT
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

No MeSH data available.