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Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.

Cheng YC, Chen HB, Su JJ, Shao CS, Wang CP, Chang CY, Wu YC - Nanoscale Res Lett (2014)

Bottom Line: Using a thin channel structure obtains excellent performance in the raised S/D structure.Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs.This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu, 30013, Taiwan, citygirl0831@hotmail.com.

ABSTRACT
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

No MeSH data available.


Device structure and detailed process flow of the fabrication. (a) The device structure for the raised S/D p-type JL-TFTs. (b) The detailed process flow of the fabrication in the raised S/D JL-TFTs. The positions A and A’ indicate the cross-section of the channel.
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Fig1: Device structure and detailed process flow of the fabrication. (a) The device structure for the raised S/D p-type JL-TFTs. (b) The detailed process flow of the fabrication in the raised S/D JL-TFTs. The positions A and A’ indicate the cross-section of the channel.

Mentions: Figure 1a schematically presents the proposed device structure of the raised S/D JL-TFT, and Figure 1b shows the detailed process flows of the fabrication in the raised S/D JL-TFT. The p-type raised S/D JL-TFT is fabricated by initially growing a 400-nm thermal silicon dioxide layer on a 6-in. silicon wafer. A 40-nm amorphous Si (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C. Then, the a-Si layer was formed by solid-phase recrystallized (SPC) process at 600°C for 24 h in nitrogen ambient. After borondifluoride (BF2) ion implantation with 30 keV at a dose of 2 × 1014 cm−2 for the p+ raised S/D doping followed by furnace annealing at 600°C for 4 h, the raised S/D is patterned by e-beam lithography. Subsequently, using the same method for the production of a-Si deposition (40 nm), the implantation (30 keV, BF2, 2 × 1014 cm−2) and the SPC process form the channel layer. While serving as a channel, the active layer was patterned by e-beam lithography and then anisotropically etched by time-controlled reactive ion etching (RIE). The patterned width of each nanosheet channel is 0.3 μm. Then, the active channel was mesa-etched by time-controlled wet etching of dilute HF to form the omega-shaped channel. Next, a sacrificial oxide as a trimming process was thermally grown at 900°C for 2 h, which consumes around 22-nm-thick poly-Si. Subsequently, the dry oxide of 20-nm thickness was deposited as the gate oxide layer, consuming around 10-nm-thick poly-Si to form a 7.35-nm-thick channel. The 150-nm-thick in situ doped n+ poly-silicon was deposited as a gate electrode and patterned by e-beam and RIE. Additionally, a 200-nm SiO2 passivation layer was deposited. Finally, a 300-nm-thick Al-Si-Cu metallization was performed and sintered at 400°C for 30 min.Figure 1


Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.

Cheng YC, Chen HB, Su JJ, Shao CS, Wang CP, Chang CY, Wu YC - Nanoscale Res Lett (2014)

Device structure and detailed process flow of the fabrication. (a) The device structure for the raised S/D p-type JL-TFTs. (b) The detailed process flow of the fabrication in the raised S/D JL-TFTs. The positions A and A’ indicate the cross-section of the channel.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4493839&req=5

Fig1: Device structure and detailed process flow of the fabrication. (a) The device structure for the raised S/D p-type JL-TFTs. (b) The detailed process flow of the fabrication in the raised S/D JL-TFTs. The positions A and A’ indicate the cross-section of the channel.
Mentions: Figure 1a schematically presents the proposed device structure of the raised S/D JL-TFT, and Figure 1b shows the detailed process flows of the fabrication in the raised S/D JL-TFT. The p-type raised S/D JL-TFT is fabricated by initially growing a 400-nm thermal silicon dioxide layer on a 6-in. silicon wafer. A 40-nm amorphous Si (a-Si) layer was deposited by low-pressure chemical vapor deposition (LPCVD) at 550°C. Then, the a-Si layer was formed by solid-phase recrystallized (SPC) process at 600°C for 24 h in nitrogen ambient. After borondifluoride (BF2) ion implantation with 30 keV at a dose of 2 × 1014 cm−2 for the p+ raised S/D doping followed by furnace annealing at 600°C for 4 h, the raised S/D is patterned by e-beam lithography. Subsequently, using the same method for the production of a-Si deposition (40 nm), the implantation (30 keV, BF2, 2 × 1014 cm−2) and the SPC process form the channel layer. While serving as a channel, the active layer was patterned by e-beam lithography and then anisotropically etched by time-controlled reactive ion etching (RIE). The patterned width of each nanosheet channel is 0.3 μm. Then, the active channel was mesa-etched by time-controlled wet etching of dilute HF to form the omega-shaped channel. Next, a sacrificial oxide as a trimming process was thermally grown at 900°C for 2 h, which consumes around 22-nm-thick poly-Si. Subsequently, the dry oxide of 20-nm thickness was deposited as the gate oxide layer, consuming around 10-nm-thick poly-Si to form a 7.35-nm-thick channel. The 150-nm-thick in situ doped n+ poly-silicon was deposited as a gate electrode and patterned by e-beam and RIE. Additionally, a 200-nm SiO2 passivation layer was deposited. Finally, a 300-nm-thick Al-Si-Cu metallization was performed and sintered at 400°C for 30 min.Figure 1

Bottom Line: Using a thin channel structure obtains excellent performance in the raised S/D structure.Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs.This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu, 30013, Taiwan, citygirl0831@hotmail.com.

ABSTRACT
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

No MeSH data available.