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Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.

Cheng YC, Chen HB, Su JJ, Shao CS, Wang CP, Chang CY, Wu YC - Nanoscale Res Lett (2014)

Bottom Line: Using a thin channel structure obtains excellent performance in the raised S/D structure.Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs.This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu, 30013, Taiwan, citygirl0831@hotmail.com.

ABSTRACT
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

No MeSH data available.


Related in: MedlinePlus

The temperature dependence of dual-gate JL-TFTs at 100°C onId-Vgcharacteristics (a-d).
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Fig10: The temperature dependence of dual-gate JL-TFTs at 100°C onId-Vgcharacteristics (a-d).

Mentions: where D = exp(x/lcrit), x is the distance from the interface, and lcrit is a fitting parameter. The mobility consists of three parts: 1) surface acoustic phonon scattering (μsurf_aps), 2) surface roughness scattering (μsurf_rs), and 3) bulk mobility with doping-dependent modification (μbulk_dop). The details are described in [14, 17]. Figure 9a shows the high off current when G1 is sweeping at 2 V and G2 is at on-state bias of −3.5 V. When the G2 is in extreme on-state, band-to-band tunneling occurs easily according to the simulation results. Figure 9b shows the pinning mechanism when G1 is sweeping and G2 is at off-state bias. When the G2 voltage approaches off-state, the valence band will be dropped off, which retards the hole transport and causes a saturation current. Figure 10 shows the temperature characteristics of the dual-gate structure. High-temperature performance is similar to that at room temperature.Figure 5


Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure.

Cheng YC, Chen HB, Su JJ, Shao CS, Wang CP, Chang CY, Wu YC - Nanoscale Res Lett (2014)

The temperature dependence of dual-gate JL-TFTs at 100°C onId-Vgcharacteristics (a-d).
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4493839&req=5

Fig10: The temperature dependence of dual-gate JL-TFTs at 100°C onId-Vgcharacteristics (a-d).
Mentions: where D = exp(x/lcrit), x is the distance from the interface, and lcrit is a fitting parameter. The mobility consists of three parts: 1) surface acoustic phonon scattering (μsurf_aps), 2) surface roughness scattering (μsurf_rs), and 3) bulk mobility with doping-dependent modification (μbulk_dop). The details are described in [14, 17]. Figure 9a shows the high off current when G1 is sweeping at 2 V and G2 is at on-state bias of −3.5 V. When the G2 is in extreme on-state, band-to-band tunneling occurs easily according to the simulation results. Figure 9b shows the pinning mechanism when G1 is sweeping and G2 is at off-state bias. When the G2 voltage approaches off-state, the valence band will be dropped off, which retards the hole transport and causes a saturation current. Figure 10 shows the temperature characteristics of the dual-gate structure. High-temperature performance is similar to that at room temperature.Figure 5

Bottom Line: Using a thin channel structure obtains excellent performance in the raised S/D structure.Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs.This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2, Kuang Fu Road, Hsinchu, 30013, Taiwan, citygirl0831@hotmail.com.

ABSTRACT
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V th in multi-V th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

No MeSH data available.


Related in: MedlinePlus