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Tunnel junction based memristors as artificial synapses.

Thomas A, Niehörster S, Fabretti S, Shepheard N, Kuschel O, Küpper K, Wollschläger J, Krzysteczko P, Chicca E - Front Neurosci (2015)

Bottom Line: The low amplitudes of the resistance change in these types of junctions are the major obstacle for their use.Here, we increased the amplitude of the resistance change from 10% up to 100%.Utilizing the memristive properties, we looked into the use of the junction structures as artificial synapses.

View Article: PubMed Central - PubMed

Affiliation: Thin Films and Physics of Nanostructures, Bielefeld University Bielefeld, Germany ; IFW Dresden, Institute for Metallic Materials Dresden, Germany.

ABSTRACT
We prepared magnesia, tantalum oxide, and barium titanate based tunnel junction structures and investigated their memristive properties. The low amplitudes of the resistance change in these types of junctions are the major obstacle for their use. Here, we increased the amplitude of the resistance change from 10% up to 100%. Utilizing the memristive properties, we looked into the use of the junction structures as artificial synapses. We observed analogs of long-term potentiation, long-term depression and spike-time dependent plasticity in these simple two terminal devices. Finally, we suggest a possible pathway of these devices toward their integration in neuromorphic systems for storing analog synaptic weights and supporting the implementation of biologically plausible learning mechanisms.

No MeSH data available.


Related in: MedlinePlus

Neuromorphic chip with contact pads for our memristors (red frames). The chip was fabricated using a standard AMS 0,35 μm CMOS process and supports the integration of memristor devices with neuromorphic synaptic and neural circuits.
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Figure 8: Neuromorphic chip with contact pads for our memristors (red frames). The chip was fabricated using a standard AMS 0,35 μm CMOS process and supports the integration of memristor devices with neuromorphic synaptic and neural circuits.

Mentions: To further demonstrate the possible integration of Ta-O memristors into existing technologies, we designed a neuromorphic chip comprised of synaptic and neural circuits as well as various test structures for the deposition of memristor devices (pads marked with red frames in Figure 8). The chip was fabricated using a standard AMS 0.35 μm CMOS process, covers an area of about 1.6 mm2 and includes neuromorphic circuits as described in Chicca et al. (2014). The test structures enable the deposition of the presented layer stacks on top of the chip and subsequent e-beam lithography as well as ion beam etching to define the junctions. The underlying synaptic circuits are the ones proposed by Indiveri et al. (2013) and this scheme supports the direct integration of the memristor by allowing the implementation of programmable synaptic weights. The corresponding simulation results are also given by the same authors (Indiveri et al., 2013).


Tunnel junction based memristors as artificial synapses.

Thomas A, Niehörster S, Fabretti S, Shepheard N, Kuschel O, Küpper K, Wollschläger J, Krzysteczko P, Chicca E - Front Neurosci (2015)

Neuromorphic chip with contact pads for our memristors (red frames). The chip was fabricated using a standard AMS 0,35 μm CMOS process and supports the integration of memristor devices with neuromorphic synaptic and neural circuits.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4493388&req=5

Figure 8: Neuromorphic chip with contact pads for our memristors (red frames). The chip was fabricated using a standard AMS 0,35 μm CMOS process and supports the integration of memristor devices with neuromorphic synaptic and neural circuits.
Mentions: To further demonstrate the possible integration of Ta-O memristors into existing technologies, we designed a neuromorphic chip comprised of synaptic and neural circuits as well as various test structures for the deposition of memristor devices (pads marked with red frames in Figure 8). The chip was fabricated using a standard AMS 0.35 μm CMOS process, covers an area of about 1.6 mm2 and includes neuromorphic circuits as described in Chicca et al. (2014). The test structures enable the deposition of the presented layer stacks on top of the chip and subsequent e-beam lithography as well as ion beam etching to define the junctions. The underlying synaptic circuits are the ones proposed by Indiveri et al. (2013) and this scheme supports the direct integration of the memristor by allowing the implementation of programmable synaptic weights. The corresponding simulation results are also given by the same authors (Indiveri et al., 2013).

Bottom Line: The low amplitudes of the resistance change in these types of junctions are the major obstacle for their use.Here, we increased the amplitude of the resistance change from 10% up to 100%.Utilizing the memristive properties, we looked into the use of the junction structures as artificial synapses.

View Article: PubMed Central - PubMed

Affiliation: Thin Films and Physics of Nanostructures, Bielefeld University Bielefeld, Germany ; IFW Dresden, Institute for Metallic Materials Dresden, Germany.

ABSTRACT
We prepared magnesia, tantalum oxide, and barium titanate based tunnel junction structures and investigated their memristive properties. The low amplitudes of the resistance change in these types of junctions are the major obstacle for their use. Here, we increased the amplitude of the resistance change from 10% up to 100%. Utilizing the memristive properties, we looked into the use of the junction structures as artificial synapses. We observed analogs of long-term potentiation, long-term depression and spike-time dependent plasticity in these simple two terminal devices. Finally, we suggest a possible pathway of these devices toward their integration in neuromorphic systems for storing analog synaptic weights and supporting the implementation of biologically plausible learning mechanisms.

No MeSH data available.


Related in: MedlinePlus