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Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

El-Desouki MM, Qasim SM, BenSaleh MS, Deen MJ - Sensors (Basel) (2015)

Bottom Line: The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz.The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area.Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

View Article: PubMed Central - PubMed

Affiliation: King Abdulaziz City for Science and Technology (KACST), Riyadh 11442, Saudi Arabia. mdesouki@kacst.edu.sa.

ABSTRACT
The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

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Schematic of the inductively source degenerated narrowband LNA.
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sensors-15-10791-f003: Schematic of the inductively source degenerated narrowband LNA.

Mentions: LNA is one of the essential building blocks of RF receivers. In this paper, the narrowband LNA is designed as an inductively source degenerated cascade structure as shown in Figure 3. The RF signal is provided by the input RF port while the bias voltage is provided by the voltage source (Vbias1). The capacitor C1 and inductor L1 are used to block the DC and AC signals respectively. The elements Lg, Ls, Cp and the NMOS transistor M1 form the input matching network of the LNA [19]. The input matching impedance of this amplifier can be expressed as [20]:(1)Zin=1s(Cgs+Cp)+s(Ls+Lg)+gmLsCgs+Cpwhere, gm is the transconductance and Cgs is the gate-source capacitance of the transistor M1.


Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

El-Desouki MM, Qasim SM, BenSaleh MS, Deen MJ - Sensors (Basel) (2015)

Schematic of the inductively source degenerated narrowband LNA.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4481954&req=5

sensors-15-10791-f003: Schematic of the inductively source degenerated narrowband LNA.
Mentions: LNA is one of the essential building blocks of RF receivers. In this paper, the narrowband LNA is designed as an inductively source degenerated cascade structure as shown in Figure 3. The RF signal is provided by the input RF port while the bias voltage is provided by the voltage source (Vbias1). The capacitor C1 and inductor L1 are used to block the DC and AC signals respectively. The elements Lg, Ls, Cp and the NMOS transistor M1 form the input matching network of the LNA [19]. The input matching impedance of this amplifier can be expressed as [20]:(1)Zin=1s(Cgs+Cp)+s(Ls+Lg)+gmLsCgs+Cpwhere, gm is the transconductance and Cgs is the gate-source capacitance of the transistor M1.

Bottom Line: The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz.The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area.Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

View Article: PubMed Central - PubMed

Affiliation: King Abdulaziz City for Science and Technology (KACST), Riyadh 11442, Saudi Arabia. mdesouki@kacst.edu.sa.

ABSTRACT
The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

Show MeSH
Related in: MedlinePlus