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Ring Counter Based ATPG for Low Transition Test Pattern Generation.

Begam VM, Baulkani S - ScientificWorldJournal (2015)

Bottom Line: Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation.The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG.Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.

View Article: PubMed Central - PubMed

Affiliation: Department of ICE, Anna University, Chennai 600 025, India.

ABSTRACT
In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.

No MeSH data available.


Modified flip flop.
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Related In: Results  -  Collection


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fig3: Modified flip flop.

Mentions: In this RC-based TPG the D-FFs are replaced by modified D-FFs (Figure 3). Initially each test pattern is equally divided into two parts as least significant bytes and most significant bytes. Half of the flip flop outputs, that is, LSB of the test pattern, are applied to CUT through bit selector LSB circuit. BSC generates partial insertion bits. The remaining (MSB) half of the test pattern must be frozen during test vector insertion using bit selector MSB circuit.


Ring Counter Based ATPG for Low Transition Test Pattern Generation.

Begam VM, Baulkani S - ScientificWorldJournal (2015)

Modified flip flop.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4446507&req=5

fig3: Modified flip flop.
Mentions: In this RC-based TPG the D-FFs are replaced by modified D-FFs (Figure 3). Initially each test pattern is equally divided into two parts as least significant bytes and most significant bytes. Half of the flip flop outputs, that is, LSB of the test pattern, are applied to CUT through bit selector LSB circuit. BSC generates partial insertion bits. The remaining (MSB) half of the test pattern must be frozen during test vector insertion using bit selector MSB circuit.

Bottom Line: Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation.The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG.Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.

View Article: PubMed Central - PubMed

Affiliation: Department of ICE, Anna University, Chennai 600 025, India.

ABSTRACT
In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.

No MeSH data available.