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A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step.

Lai WT, Yang KC, Hsu TC, Liao PH, George T, Li PW - Nanoscale Res Lett (2015)

Bottom Line: The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials.Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions.We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronics Engineering, National ChiaoTung University, HsinChu, 300 Taiwan.

ABSTRACT
We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 × 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

No MeSH data available.


Related in: MedlinePlus

a Transfer and b output characteristics of the heterostructured SiO2/Ge QD/SiO2/SiGe n-MOSFETs measured at T = 77–300 K. High Ion/Ioff ratio >106 and low off-state leakage of Ioff <10−13 A/μm are achieved
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Fig3: a Transfer and b output characteristics of the heterostructured SiO2/Ge QD/SiO2/SiGe n-MOSFETs measured at T = 77–300 K. High Ion/Ioff ratio >106 and low off-state leakage of Ioff <10−13 A/μm are achieved

Mentions: Id-Vg of the heterostructured Ge QD/SiO2/SiGe channel nMOSFETs show very low off-state leakage of Ioff ≅ 10−13 A/μm. A superior on-off current ratio of Ion/Ioff >106 and good switching behavior for S.S. of 195 mV/dec at T = 300 K were also measured (Fig. 3a). This low value of Ioff leakage as well as the high Ion/Ioff ratio is attributable to the high crystalline quality of the SiGe channel and good interface properties for the thin SiO2 and SiGe channel. The Id-Vg characteristics were measured at T = 77–300 K to estimate S.S. from its dependence on temperature. Decreasing the operating temperature from 300 to 77 K results in significant, twofold enhancement of the on-state drive current (Fig. 3b). The S.S. improves from 195 to 105 mV/dec as a result of the suppressed phonon scattering. Dit estimated from the S.S. value for n-MOSFETs is approximately 4 × 1011 cm−2 eV−1 at T = 300 K, which is in good agreement with estimates derived from the high-/low-frequency C-V characteristics. As mentioned previously, the conducting channel connecting source and drain indeed consists of the prime SiGe shell in series with the second Si inversion layer that would be sequentially turned on due to the difference in the EOT of gate dielectric layers. It would require a greater gate voltage swing (i.e., larger S.S.) to completely turn on the entire composited channel than the solely SiGe shell. We envisage that significant improvements in S.S. and switching performance are achievable through reducing the parasitic Si channel via shrinking the channel length and increasing the pillar (QD) density within the channel.Fig. 3


A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step.

Lai WT, Yang KC, Hsu TC, Liao PH, George T, Li PW - Nanoscale Res Lett (2015)

a Transfer and b output characteristics of the heterostructured SiO2/Ge QD/SiO2/SiGe n-MOSFETs measured at T = 77–300 K. High Ion/Ioff ratio >106 and low off-state leakage of Ioff <10−13 A/μm are achieved
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4440870&req=5

Fig3: a Transfer and b output characteristics of the heterostructured SiO2/Ge QD/SiO2/SiGe n-MOSFETs measured at T = 77–300 K. High Ion/Ioff ratio >106 and low off-state leakage of Ioff <10−13 A/μm are achieved
Mentions: Id-Vg of the heterostructured Ge QD/SiO2/SiGe channel nMOSFETs show very low off-state leakage of Ioff ≅ 10−13 A/μm. A superior on-off current ratio of Ion/Ioff >106 and good switching behavior for S.S. of 195 mV/dec at T = 300 K were also measured (Fig. 3a). This low value of Ioff leakage as well as the high Ion/Ioff ratio is attributable to the high crystalline quality of the SiGe channel and good interface properties for the thin SiO2 and SiGe channel. The Id-Vg characteristics were measured at T = 77–300 K to estimate S.S. from its dependence on temperature. Decreasing the operating temperature from 300 to 77 K results in significant, twofold enhancement of the on-state drive current (Fig. 3b). The S.S. improves from 195 to 105 mV/dec as a result of the suppressed phonon scattering. Dit estimated from the S.S. value for n-MOSFETs is approximately 4 × 1011 cm−2 eV−1 at T = 300 K, which is in good agreement with estimates derived from the high-/low-frequency C-V characteristics. As mentioned previously, the conducting channel connecting source and drain indeed consists of the prime SiGe shell in series with the second Si inversion layer that would be sequentially turned on due to the difference in the EOT of gate dielectric layers. It would require a greater gate voltage swing (i.e., larger S.S.) to completely turn on the entire composited channel than the solely SiGe shell. We envisage that significant improvements in S.S. and switching performance are achievable through reducing the parasitic Si channel via shrinking the channel length and increasing the pillar (QD) density within the channel.Fig. 3

Bottom Line: The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials.Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions.We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronics Engineering, National ChiaoTung University, HsinChu, 300 Taiwan.

ABSTRACT
We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 × 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

No MeSH data available.


Related in: MedlinePlus