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A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step.

Lai WT, Yang KC, Hsu TC, Liao PH, George T, Li PW - Nanoscale Res Lett (2015)

Bottom Line: The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 × 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs).Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions.We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronics Engineering, National ChiaoTung University, HsinChu, 300 Taiwan.

ABSTRACT
We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 × 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

No MeSH data available.


Related in: MedlinePlus

a Cross-sectional transmission electron microscopy (CTEM) images as well as EDX elemental b line-scan spectra and c X-ray mapping micrographs of a SiO2/Ge QD/SiO2/SiGe shell heterostructure over the Si substrate. d Selected area diffraction patterns were generated by applying a fast Fourier transform to the local high-resolution CTEM images of the SiGe shell. The interplanar spacing is approximately 3.16 nm, corresponding to Si0.28Ge0.72 {111} planes
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Fig1: a Cross-sectional transmission electron microscopy (CTEM) images as well as EDX elemental b line-scan spectra and c X-ray mapping micrographs of a SiO2/Ge QD/SiO2/SiGe shell heterostructure over the Si substrate. d Selected area diffraction patterns were generated by applying a fast Fourier transform to the local high-resolution CTEM images of the SiGe shell. The interplanar spacing is approximately 3.16 nm, corresponding to Si0.28Ge0.72 {111} planes

Mentions: The fabrication starts with tri-layer, sequential low-pressure chemical vapor deposition of 25-nm-thick Si3N4, 70-nm-thick poly-Si0.85Ge0.15, and finally, a capping layer of a 5-nm-thick SiO2 over a Si substrate. The topmost, capping SiO2 and the poly-Si0.85Ge0.15 layers are lithographically defined to create 240-nm diameter, nanocylindrical pillars. The SiGe pillar density is approximately 1 × 109 cm−2 over the buffer Si3N4 layers. Next, the nanopatterned structure is subjected to thermal oxidation at 900 °C within an H2O ambient producing 90-nm diameter, spherical Ge QDs that migrate into the buffer Si3N4 layer [17, 18], as shown in Fig. 1a. Next, an Al top gate (with an area of 75 μm × 75 μm) and substrate electrodes are fabricated over the Ge QD array and the backside of the Si substrate, respectively. A final, forming gas anneal at 400 °C completes the fabrication of the Al-SiO2/Ge QD/SiO2-SiGe MOS capacitors. Additional processes for defining the Al gate and As-doped source/drain (S/D) electrodes are conducted for the fabrication of floating gate MOSFETs. The channel length (Lg) and width (W) are 3 and 50 μm, respectively. High-resolution, cross-sectional transmission electron microscopy (CTEM) and energy dispersive X-ray (EDX) spectroscopy were used to examine the crystallinity, interfacial morphology, and chemical purity of the Ge QD/SiO2/Si heterostructures. Electrical and interfacial properties of SiO2/Ge QD/SiO2/SiGe MOS devices were measured using frequency-dependent capacitance-voltage(C-V) and current–voltage (I-V) characterization over a range of temperatures. Pulse I-V measurements were also conducted to characterize the floating gate memory devices.Fig. 1


A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step.

Lai WT, Yang KC, Hsu TC, Liao PH, George T, Li PW - Nanoscale Res Lett (2015)

a Cross-sectional transmission electron microscopy (CTEM) images as well as EDX elemental b line-scan spectra and c X-ray mapping micrographs of a SiO2/Ge QD/SiO2/SiGe shell heterostructure over the Si substrate. d Selected area diffraction patterns were generated by applying a fast Fourier transform to the local high-resolution CTEM images of the SiGe shell. The interplanar spacing is approximately 3.16 nm, corresponding to Si0.28Ge0.72 {111} planes
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4440870&req=5

Fig1: a Cross-sectional transmission electron microscopy (CTEM) images as well as EDX elemental b line-scan spectra and c X-ray mapping micrographs of a SiO2/Ge QD/SiO2/SiGe shell heterostructure over the Si substrate. d Selected area diffraction patterns were generated by applying a fast Fourier transform to the local high-resolution CTEM images of the SiGe shell. The interplanar spacing is approximately 3.16 nm, corresponding to Si0.28Ge0.72 {111} planes
Mentions: The fabrication starts with tri-layer, sequential low-pressure chemical vapor deposition of 25-nm-thick Si3N4, 70-nm-thick poly-Si0.85Ge0.15, and finally, a capping layer of a 5-nm-thick SiO2 over a Si substrate. The topmost, capping SiO2 and the poly-Si0.85Ge0.15 layers are lithographically defined to create 240-nm diameter, nanocylindrical pillars. The SiGe pillar density is approximately 1 × 109 cm−2 over the buffer Si3N4 layers. Next, the nanopatterned structure is subjected to thermal oxidation at 900 °C within an H2O ambient producing 90-nm diameter, spherical Ge QDs that migrate into the buffer Si3N4 layer [17, 18], as shown in Fig. 1a. Next, an Al top gate (with an area of 75 μm × 75 μm) and substrate electrodes are fabricated over the Ge QD array and the backside of the Si substrate, respectively. A final, forming gas anneal at 400 °C completes the fabrication of the Al-SiO2/Ge QD/SiO2-SiGe MOS capacitors. Additional processes for defining the Al gate and As-doped source/drain (S/D) electrodes are conducted for the fabrication of floating gate MOSFETs. The channel length (Lg) and width (W) are 3 and 50 μm, respectively. High-resolution, cross-sectional transmission electron microscopy (CTEM) and energy dispersive X-ray (EDX) spectroscopy were used to examine the crystallinity, interfacial morphology, and chemical purity of the Ge QD/SiO2/Si heterostructures. Electrical and interfacial properties of SiO2/Ge QD/SiO2/SiGe MOS devices were measured using frequency-dependent capacitance-voltage(C-V) and current–voltage (I-V) characterization over a range of temperatures. Pulse I-V measurements were also conducted to characterize the floating gate memory devices.Fig. 1

Bottom Line: The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 × 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs).Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions.We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronics Engineering, National ChiaoTung University, HsinChu, 300 Taiwan.

ABSTRACT
We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 × 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

No MeSH data available.


Related in: MedlinePlus