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A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm.

Guo X, Wang H, Devabhaktuni V - ISRN Bioinform (2012)

Bottom Line: In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle.Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit.These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures.

View Article: PubMed Central - PubMed

Affiliation: Electrical Engineering and Computer Science Department, The University of Toledo, MS.308, 2801 W. Bancroft Street, Toledo, OH 43607, USA.

ABSTRACT
A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle. Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit. These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures.

No MeSH data available.


Parallel architecture of multiple hits finder array and hits combination block.
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fig8: Parallel architecture of multiple hits finder array and hits combination block.

Mentions: Because Multiple Hits Detection Module can detect multiple hits in one internal clock cycle, multiple modules working together in parallel speeds-up hit detection. In order to construct a longer array, many Multiple Hits Detection Modules are connected serially. Figure 8 shows the way of the connection.


A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm.

Guo X, Wang H, Devabhaktuni V - ISRN Bioinform (2012)

Parallel architecture of multiple hits finder array and hits combination block.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4417556&req=5

fig8: Parallel architecture of multiple hits finder array and hits combination block.
Mentions: Because Multiple Hits Detection Module can detect multiple hits in one internal clock cycle, multiple modules working together in parallel speeds-up hit detection. In order to construct a longer array, many Multiple Hits Detection Modules are connected serially. Figure 8 shows the way of the connection.

Bottom Line: In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle.Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit.These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures.

View Article: PubMed Central - PubMed

Affiliation: Electrical Engineering and Computer Science Department, The University of Toledo, MS.308, 2801 W. Bancroft Street, Toledo, OH 43607, USA.

ABSTRACT
A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle. Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit. These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures.

No MeSH data available.