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Reconfigurable Boolean logic using magnetic single-electron transistors.

Gonzalez-Zalba MF, Ciccarelli C, Zarbo LP, Irvine AC, Campion RC, Gallagher BL, Jungwirth T, Ferguson AJ, Wunderlich J - PLoS ONE (2015)

Bottom Line: We show that we can arbitrarily reprogram the function of the device from an n-type SET for in-plane magnetization of the GaMnAs layer to p-type SET for out-of-plane magnetization orientation.Moreover, we demonstrate a set of reprogrammable Boolean gates and its logical complement at the single device level.Finally, we propose two sets of reconfigurable binary gates using combinations of two MSETs in a pull-down network.

View Article: PubMed Central - PubMed

Affiliation: Hitachi Cambridge Laboratory, Cambridge CB3 0HE, United Kingdom.

ABSTRACT
We propose a novel hybrid single-electron device for reprogrammable low-power logic operations, the magnetic single-electron transistor (MSET). The device consists of an aluminium single-electron transistor with a GaMnAs magnetic back-gate. Changing between different logic gate functions is realized by reorienting the magnetic moments of the magnetic layer, which induces a voltage shift on the Coulomb blockade oscillations of the MSET. We show that we can arbitrarily reprogram the function of the device from an n-type SET for in-plane magnetization of the GaMnAs layer to p-type SET for out-of-plane magnetization orientation. Moreover, we demonstrate a set of reprogrammable Boolean gates and its logical complement at the single device level. Finally, we propose two sets of reconfigurable binary gates using combinations of two MSETs in a pull-down network.

No MeSH data available.


Single-device logic.(a) Vds − Vgs map of the drain current for ϕ = 0° showing the characteristic Coulomb diamonds. Red and blue frames sketch the implemented logic gates for ϕ = 0° and 90° respectively. (b-c) AND-OR set of reprogrammable logic gates. AND gate implemented at ϕ = 0° (b) and OR gate at ϕ = 90° (c) with Vds (input A) 0(1) defined as −132(−220) μV and Vgs (input B) 0(1) defined as −96(0) μV. (d-e) NAND-NOR set of reprogrammable logic gates. NAND gate implemented at ϕ = 0° (d) and NOR gate at ϕ = 90° (e) with Vsd (input A) 0(1) defined as 220(132) μV and Vgs (input B) 0(1) defined as 128(224) μV.
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pone.0125142.g003: Single-device logic.(a) Vds − Vgs map of the drain current for ϕ = 0° showing the characteristic Coulomb diamonds. Red and blue frames sketch the implemented logic gates for ϕ = 0° and 90° respectively. (b-c) AND-OR set of reprogrammable logic gates. AND gate implemented at ϕ = 0° (b) and OR gate at ϕ = 90° (c) with Vds (input A) 0(1) defined as −132(−220) μV and Vgs (input B) 0(1) defined as −96(0) μV. (d-e) NAND-NOR set of reprogrammable logic gates. NAND gate implemented at ϕ = 0° (d) and NOR gate at ϕ = 90° (e) with Vsd (input A) 0(1) defined as 220(132) μV and Vgs (input B) 0(1) defined as 128(224) μV.

Mentions: We now focus on the logic design that could be implemented at the single device level. It has been shown that any Boolean function of two variables can be implemented on a SET [25]. In this letter, by making use of the magnetic mode of operation, we demonstrate two sets of reprogrammable logic gates. The inputs in this case are the drain voltage (input A) and the gate voltage (input B) and the output is the drain current. In Fig 3(a) we plot the Vds − Vgs diagram of the MSET showing the characteristic Coulomb diamonds at ϕ = 0°. Overimposed, we schematically show two logic gates framed in red AND and NAND. The output is drawn as en empty dot if the results is 0 (low current level) and a full dot if the results is 1 (high current level). Upon changing the magnetization angle to ϕ = 90°, the whole diagram is shifted horizontally by ΔVgs = -150 μV and, therefore, at the same input voltages the gate output changes to the two blue-framed logic gates, from (N)AND to (N)OR as depicted by the arrow. The reconfigurable logic gates are demonstrated in the histograms in Fig 3(b)–3(e). In order to discriminate between logic outputs 0 and 1 we select the low(high) current threshold at Ids = 80(90) pA. In Fig 3(b) we represent a histogram of the current output for an AND gate implemented on the edge of the Coulomb diamond. By rotating the magnetization to the in-plane direction (ϕ = 90°) the Coulomb diamonds shift and the logic gate switches function to OR (Fig 3(c)). Moreover, in Fig 3(d) and 3(e) we demonstrate the logical complement set of reprogrammable Boolean gates. The set switches between NAND (ϕ = 0°) and NOR (ϕ = 90°) logic gates.


Reconfigurable Boolean logic using magnetic single-electron transistors.

Gonzalez-Zalba MF, Ciccarelli C, Zarbo LP, Irvine AC, Campion RC, Gallagher BL, Jungwirth T, Ferguson AJ, Wunderlich J - PLoS ONE (2015)

Single-device logic.(a) Vds − Vgs map of the drain current for ϕ = 0° showing the characteristic Coulomb diamonds. Red and blue frames sketch the implemented logic gates for ϕ = 0° and 90° respectively. (b-c) AND-OR set of reprogrammable logic gates. AND gate implemented at ϕ = 0° (b) and OR gate at ϕ = 90° (c) with Vds (input A) 0(1) defined as −132(−220) μV and Vgs (input B) 0(1) defined as −96(0) μV. (d-e) NAND-NOR set of reprogrammable logic gates. NAND gate implemented at ϕ = 0° (d) and NOR gate at ϕ = 90° (e) with Vsd (input A) 0(1) defined as 220(132) μV and Vgs (input B) 0(1) defined as 128(224) μV.
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Related In: Results  -  Collection

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Show All Figures
getmorefigures.php?uid=PMC4414357&req=5

pone.0125142.g003: Single-device logic.(a) Vds − Vgs map of the drain current for ϕ = 0° showing the characteristic Coulomb diamonds. Red and blue frames sketch the implemented logic gates for ϕ = 0° and 90° respectively. (b-c) AND-OR set of reprogrammable logic gates. AND gate implemented at ϕ = 0° (b) and OR gate at ϕ = 90° (c) with Vds (input A) 0(1) defined as −132(−220) μV and Vgs (input B) 0(1) defined as −96(0) μV. (d-e) NAND-NOR set of reprogrammable logic gates. NAND gate implemented at ϕ = 0° (d) and NOR gate at ϕ = 90° (e) with Vsd (input A) 0(1) defined as 220(132) μV and Vgs (input B) 0(1) defined as 128(224) μV.
Mentions: We now focus on the logic design that could be implemented at the single device level. It has been shown that any Boolean function of two variables can be implemented on a SET [25]. In this letter, by making use of the magnetic mode of operation, we demonstrate two sets of reprogrammable logic gates. The inputs in this case are the drain voltage (input A) and the gate voltage (input B) and the output is the drain current. In Fig 3(a) we plot the Vds − Vgs diagram of the MSET showing the characteristic Coulomb diamonds at ϕ = 0°. Overimposed, we schematically show two logic gates framed in red AND and NAND. The output is drawn as en empty dot if the results is 0 (low current level) and a full dot if the results is 1 (high current level). Upon changing the magnetization angle to ϕ = 90°, the whole diagram is shifted horizontally by ΔVgs = -150 μV and, therefore, at the same input voltages the gate output changes to the two blue-framed logic gates, from (N)AND to (N)OR as depicted by the arrow. The reconfigurable logic gates are demonstrated in the histograms in Fig 3(b)–3(e). In order to discriminate between logic outputs 0 and 1 we select the low(high) current threshold at Ids = 80(90) pA. In Fig 3(b) we represent a histogram of the current output for an AND gate implemented on the edge of the Coulomb diamond. By rotating the magnetization to the in-plane direction (ϕ = 90°) the Coulomb diamonds shift and the logic gate switches function to OR (Fig 3(c)). Moreover, in Fig 3(d) and 3(e) we demonstrate the logical complement set of reprogrammable Boolean gates. The set switches between NAND (ϕ = 0°) and NOR (ϕ = 90°) logic gates.

Bottom Line: We show that we can arbitrarily reprogram the function of the device from an n-type SET for in-plane magnetization of the GaMnAs layer to p-type SET for out-of-plane magnetization orientation.Moreover, we demonstrate a set of reprogrammable Boolean gates and its logical complement at the single device level.Finally, we propose two sets of reconfigurable binary gates using combinations of two MSETs in a pull-down network.

View Article: PubMed Central - PubMed

Affiliation: Hitachi Cambridge Laboratory, Cambridge CB3 0HE, United Kingdom.

ABSTRACT
We propose a novel hybrid single-electron device for reprogrammable low-power logic operations, the magnetic single-electron transistor (MSET). The device consists of an aluminium single-electron transistor with a GaMnAs magnetic back-gate. Changing between different logic gate functions is realized by reorienting the magnetic moments of the magnetic layer, which induces a voltage shift on the Coulomb blockade oscillations of the MSET. We show that we can arbitrarily reprogram the function of the device from an n-type SET for in-plane magnetization of the GaMnAs layer to p-type SET for out-of-plane magnetization orientation. Moreover, we demonstrate a set of reprogrammable Boolean gates and its logical complement at the single device level. Finally, we propose two sets of reconfigurable binary gates using combinations of two MSETs in a pull-down network.

No MeSH data available.