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Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

Wang Z, Al-Jawhari HA, Nayak PK, Caraveo-Frescas JA, Wei N, Hedhili MN, Alshareef HN - Sci Rep (2015)

Bottom Line: The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase.The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide.Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

View Article: PubMed Central - PubMed

Affiliation: Materials Science and Engineering, King Abdullah University of Science &Technology (KAUST), Thuwal 23955-6900, Saudi Arabia.

ABSTRACT
In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

No MeSH data available.


Related in: MedlinePlus

Performances of CMOS inverters.(a) Voltage transfer and gain characteristics of CMOS inverters with variable channel size ratios. (b) Voltage transfer curves of optimized CMOS inverter.
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f3: Performances of CMOS inverters.(a) Voltage transfer and gain characteristics of CMOS inverters with variable channel size ratios. (b) Voltage transfer curves of optimized CMOS inverter.

Mentions: The schematic illustration of our CMOS inverter is presented in Figure 1(e). The ITO bottom gate layer was connected to the input terminal as Vin. The source electrode of p-type TFT was used as the Vdd terminal. The source electrode of n-type TFT was applied as the Vss terminal, which was connected to an Agilent high performance ground unit. Finally, the output terminal (Vout) was built by connecting the drain electrodes of both p- and n-type TFTs. In order to adjust the transition voltage (VM, maximum gain voltage) of CMOS inverter, load ratio (β = μ × W/L) of each type TFT was accurately measured and calculated. Finally, by selecting large (W/L)n/(W/L)p ratio, compatible p- and n-type load ratios (βn/βp ~ 1) were achieved and the VM was located at about Vdd/2. The voltage transfer curves (VTC) of the selected CMOS inverters are shown in Figure 3(a). The VM is sensitive to the βn/βp and the Vth of each type oxide TFT. Gain of CMOS inverter was calculated by evaluating the negative slope (−dVout/dVin) of each VTC curve and the results are shown in Figure 3(a), our CMOS inverters show a maximum gain of ~4. The VTC curve of the optimized CMOS inverter under linearly increased Vdd is presented in Figure 3(b). We attribute the low gain value to the large SS and the low Ion/Ioff of TFTs, which may be optimized by replacing the dielectric layer, stacking a passivation layer on top of device.


Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

Wang Z, Al-Jawhari HA, Nayak PK, Caraveo-Frescas JA, Wei N, Hedhili MN, Alshareef HN - Sci Rep (2015)

Performances of CMOS inverters.(a) Voltage transfer and gain characteristics of CMOS inverters with variable channel size ratios. (b) Voltage transfer curves of optimized CMOS inverter.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4402970&req=5

f3: Performances of CMOS inverters.(a) Voltage transfer and gain characteristics of CMOS inverters with variable channel size ratios. (b) Voltage transfer curves of optimized CMOS inverter.
Mentions: The schematic illustration of our CMOS inverter is presented in Figure 1(e). The ITO bottom gate layer was connected to the input terminal as Vin. The source electrode of p-type TFT was used as the Vdd terminal. The source electrode of n-type TFT was applied as the Vss terminal, which was connected to an Agilent high performance ground unit. Finally, the output terminal (Vout) was built by connecting the drain electrodes of both p- and n-type TFTs. In order to adjust the transition voltage (VM, maximum gain voltage) of CMOS inverter, load ratio (β = μ × W/L) of each type TFT was accurately measured and calculated. Finally, by selecting large (W/L)n/(W/L)p ratio, compatible p- and n-type load ratios (βn/βp ~ 1) were achieved and the VM was located at about Vdd/2. The voltage transfer curves (VTC) of the selected CMOS inverters are shown in Figure 3(a). The VM is sensitive to the βn/βp and the Vth of each type oxide TFT. Gain of CMOS inverter was calculated by evaluating the negative slope (−dVout/dVin) of each VTC curve and the results are shown in Figure 3(a), our CMOS inverters show a maximum gain of ~4. The VTC curve of the optimized CMOS inverter under linearly increased Vdd is presented in Figure 3(b). We attribute the low gain value to the large SS and the low Ion/Ioff of TFTs, which may be optimized by replacing the dielectric layer, stacking a passivation layer on top of device.

Bottom Line: The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase.The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide.Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

View Article: PubMed Central - PubMed

Affiliation: Materials Science and Engineering, King Abdullah University of Science &Technology (KAUST), Thuwal 23955-6900, Saudi Arabia.

ABSTRACT
In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

No MeSH data available.


Related in: MedlinePlus