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Integrating reconfigurable hardware-based grid for high performance computing.

Dondo Gazzano J, Sanchez Molina F, Rincon F, López JC - ScientificWorldJournal (2015)

Bottom Line: The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use.An example application and a comparison with other hardware and software implementations are shown.Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

View Article: PubMed Central - PubMed

Affiliation: Escuela Superior de Informatica, Universidad de Castilla-La Mancha, 13071 Ciudad Real, Spain.

ABSTRACT
FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

No MeSH data available.


Processor Role Description.
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Related In: Results  -  Collection


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alg3: Processor Role Description.

Mentions: Processing role was divided into two parts. One is devoted to store partial data received from data controller and the other is for multiplication process. The stoSubMatrix method stores partial data in local memory starting from the memory address indicated by pos parameter. The parameters sizeXp indicates the total amount of submatrix elements, and Number_of_vectors indicates the number of data vector sent to the processing element, whereas data parameter indicates the value of the corresponding matrix element (see Algorithm 3 Processor Role description).


Integrating reconfigurable hardware-based grid for high performance computing.

Dondo Gazzano J, Sanchez Molina F, Rincon F, López JC - ScientificWorldJournal (2015)

Processor Role Description.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4385699&req=5

alg3: Processor Role Description.
Mentions: Processing role was divided into two parts. One is devoted to store partial data received from data controller and the other is for multiplication process. The stoSubMatrix method stores partial data in local memory starting from the memory address indicated by pos parameter. The parameters sizeXp indicates the total amount of submatrix elements, and Number_of_vectors indicates the number of data vector sent to the processing element, whereas data parameter indicates the value of the corresponding matrix element (see Algorithm 3 Processor Role description).

Bottom Line: The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use.An example application and a comparison with other hardware and software implementations are shown.Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

View Article: PubMed Central - PubMed

Affiliation: Escuela Superior de Informatica, Universidad de Castilla-La Mancha, 13071 Ciudad Real, Spain.

ABSTRACT
FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

No MeSH data available.