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Integrating reconfigurable hardware-based grid for high performance computing.

Dondo Gazzano J, Sanchez Molina F, Rincon F, López JC - ScientificWorldJournal (2015)

Bottom Line: The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use.An example application and a comparison with other hardware and software implementations are shown.Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

View Article: PubMed Central - PubMed

Affiliation: Escuela Superior de Informatica, Universidad de Castilla-La Mancha, 13071 Ciudad Real, Spain.

ABSTRACT
FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

No MeSH data available.


Communication time in each part of the communication process.
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Related In: Results  -  Collection


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fig9: Communication time in each part of the communication process.

Mentions: Regarding communication performance, the first analysis was the evaluation of the efficiency of R-Grid protocol. The results are depicted in Figure 8 with respect to the size of communication packets. In the graph, it can be observed that the header of the message has low overhead from 90 bytes, reaching an efficiency of 75%. Figure 9 shows the time consumed during different size packets transmission in each part of the communication mechanism of the computational node. The reception and transmission time (delivery time) represent the minimum time obtained if the network could satisfy the internal bandwidth. Processing time represents the time consumed in packet processing in a component performing echo function. Physical media time represents the transmission time for a 1 Gb Ethernet network. Total time includes reception, transmission, and processing time. As can be observed, the network communication time is a limiting factor to deliver data between remote processing elements.


Integrating reconfigurable hardware-based grid for high performance computing.

Dondo Gazzano J, Sanchez Molina F, Rincon F, López JC - ScientificWorldJournal (2015)

Communication time in each part of the communication process.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4385699&req=5

fig9: Communication time in each part of the communication process.
Mentions: Regarding communication performance, the first analysis was the evaluation of the efficiency of R-Grid protocol. The results are depicted in Figure 8 with respect to the size of communication packets. In the graph, it can be observed that the header of the message has low overhead from 90 bytes, reaching an efficiency of 75%. Figure 9 shows the time consumed during different size packets transmission in each part of the communication mechanism of the computational node. The reception and transmission time (delivery time) represent the minimum time obtained if the network could satisfy the internal bandwidth. Processing time represents the time consumed in packet processing in a component performing echo function. Physical media time represents the transmission time for a 1 Gb Ethernet network. Total time includes reception, transmission, and processing time. As can be observed, the network communication time is a limiting factor to deliver data between remote processing elements.

Bottom Line: The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use.An example application and a comparison with other hardware and software implementations are shown.Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

View Article: PubMed Central - PubMed

Affiliation: Escuela Superior de Informatica, Universidad de Castilla-La Mancha, 13071 Ciudad Real, Spain.

ABSTRACT
FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

No MeSH data available.