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Break-before-make CMOS inverter for power-efficient delay implementation.

Puhan J, Raič D, Tuma T, Bűrmen Á - ScientificWorldJournal (2014)

Bottom Line: It provides differences in the dynamic response so that the direct-path current in the next stage is reduced.The energy (charge) per delay is reduced up to 40%.The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

View Article: PubMed Central - PubMed

Affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.

ABSTRACT
A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

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BBM delay cell with biased NMOS current discharge.
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Related In: Results  -  Collection


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fig14: BBM delay cell with biased NMOS current discharge.

Mentions: Two potential topology modifications not requiring the feedback are given in Figures 14 and 15. The AND gate delay therefore does not affect the width of the generated pulse. The price for removing the feedback is an increased number of transistors, which causes higher charge consumption compared to the feedback implementation from Figure 13.


Break-before-make CMOS inverter for power-efficient delay implementation.

Puhan J, Raič D, Tuma T, Bűrmen Á - ScientificWorldJournal (2014)

BBM delay cell with biased NMOS current discharge.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4265520&req=5

fig14: BBM delay cell with biased NMOS current discharge.
Mentions: Two potential topology modifications not requiring the feedback are given in Figures 14 and 15. The AND gate delay therefore does not affect the width of the generated pulse. The price for removing the feedback is an increased number of transistors, which causes higher charge consumption compared to the feedback implementation from Figure 13.

Bottom Line: It provides differences in the dynamic response so that the direct-path current in the next stage is reduced.The energy (charge) per delay is reduced up to 40%.The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

View Article: PubMed Central - PubMed

Affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.

ABSTRACT
A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Show MeSH
Related in: MedlinePlus