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Break-before-make CMOS inverter for power-efficient delay implementation.

Puhan J, Raič D, Tuma T, Bűrmen Á - ScientificWorldJournal (2014)

Bottom Line: It provides differences in the dynamic response so that the direct-path current in the next stage is reduced.The performance of the modified CMOS inverter chain is compared to standard implementation for various delays.The energy (charge) per delay is reduced up to 40%.

View Article: PubMed Central - PubMed

Affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.

ABSTRACT
A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

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Delay line implemented with BBM delay dells.
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fig12: Delay line implemented with BBM delay dells.

Mentions: Dual-ramp BBM delay cells can be used for constructing low-power delay lines. All that needs to be done is to replace standard delay elements with proposed ones, as shown in Figure 12. The number of stages in one delay element Tp can vary depending on the required delay.


Break-before-make CMOS inverter for power-efficient delay implementation.

Puhan J, Raič D, Tuma T, Bűrmen Á - ScientificWorldJournal (2014)

Delay line implemented with BBM delay dells.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4265520&req=5

fig12: Delay line implemented with BBM delay dells.
Mentions: Dual-ramp BBM delay cells can be used for constructing low-power delay lines. All that needs to be done is to replace standard delay elements with proposed ones, as shown in Figure 12. The number of stages in one delay element Tp can vary depending on the required delay.

Bottom Line: It provides differences in the dynamic response so that the direct-path current in the next stage is reduced.The performance of the modified CMOS inverter chain is compared to standard implementation for various delays.The energy (charge) per delay is reduced up to 40%.

View Article: PubMed Central - PubMed

Affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.

ABSTRACT
A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Show MeSH