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Break-before-make CMOS inverter for power-efficient delay implementation.

Puhan J, Raič D, Tuma T, Bűrmen Á - ScientificWorldJournal (2014)

Bottom Line: It provides differences in the dynamic response so that the direct-path current in the next stage is reduced.The energy (charge) per delay is reduced up to 40%.The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

View Article: PubMed Central - PubMed

Affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.

ABSTRACT
A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

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Third stage drain currents obtained with SPICE simulation for Tp = 750 ps (sizing: std. wP1 = 220 nm, lP1 = 370 nm, wN1 = 220 nm, lN1 = 880 nm, wP2 = 880 nm, lP2 = 730 nm, wN2 = 1.05 μm, lN2 = 1.32 μm; PtNf wP1 = 220 nm, lP1 = 740 nm, wN1 = 390 nm, lN1 = 180 nm, wPt = 220 nm, lPt = 350 nm, wNf = 220 nm, lNf = 950 nm, wP2 = 220 nm, lP2 = 180 nm, wN2 = 220 nm, and lN2 = 220 nm).
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fig11: Third stage drain currents obtained with SPICE simulation for Tp = 750 ps (sizing: std. wP1 = 220 nm, lP1 = 370 nm, wN1 = 220 nm, lN1 = 880 nm, wP2 = 880 nm, lP2 = 730 nm, wN2 = 1.05 μm, lN2 = 1.32 μm; PtNf wP1 = 220 nm, lP1 = 740 nm, wN1 = 390 nm, lN1 = 180 nm, wPt = 220 nm, lPt = 350 nm, wNf = 220 nm, lNf = 950 nm, wP2 = 220 nm, lP2 = 180 nm, wN2 = 220 nm, and lN2 = 220 nm).

Mentions: Elimination of static consumption can be observed in the third stage. It is the only stage actually driven by time-skewed signals. Drain currents for Tp = 750 ps sizing are depicted in Figure 11. Similar current transients can be observed with other BBM topologies and delays. The large direct-path current in the standard topology (shadowed) is almost completely eliminated in the PtNf topology. The optimization procedure obtained the required delay with large channel lengths in the second stage. This means that the bulk of the delay is caused by the third stage gate capacitances.


Break-before-make CMOS inverter for power-efficient delay implementation.

Puhan J, Raič D, Tuma T, Bűrmen Á - ScientificWorldJournal (2014)

Third stage drain currents obtained with SPICE simulation for Tp = 750 ps (sizing: std. wP1 = 220 nm, lP1 = 370 nm, wN1 = 220 nm, lN1 = 880 nm, wP2 = 880 nm, lP2 = 730 nm, wN2 = 1.05 μm, lN2 = 1.32 μm; PtNf wP1 = 220 nm, lP1 = 740 nm, wN1 = 390 nm, lN1 = 180 nm, wPt = 220 nm, lPt = 350 nm, wNf = 220 nm, lNf = 950 nm, wP2 = 220 nm, lP2 = 180 nm, wN2 = 220 nm, and lN2 = 220 nm).
© Copyright Policy - open-access
Related In: Results  -  Collection

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getmorefigures.php?uid=PMC4265520&req=5

fig11: Third stage drain currents obtained with SPICE simulation for Tp = 750 ps (sizing: std. wP1 = 220 nm, lP1 = 370 nm, wN1 = 220 nm, lN1 = 880 nm, wP2 = 880 nm, lP2 = 730 nm, wN2 = 1.05 μm, lN2 = 1.32 μm; PtNf wP1 = 220 nm, lP1 = 740 nm, wN1 = 390 nm, lN1 = 180 nm, wPt = 220 nm, lPt = 350 nm, wNf = 220 nm, lNf = 950 nm, wP2 = 220 nm, lP2 = 180 nm, wN2 = 220 nm, and lN2 = 220 nm).
Mentions: Elimination of static consumption can be observed in the third stage. It is the only stage actually driven by time-skewed signals. Drain currents for Tp = 750 ps sizing are depicted in Figure 11. Similar current transients can be observed with other BBM topologies and delays. The large direct-path current in the standard topology (shadowed) is almost completely eliminated in the PtNf topology. The optimization procedure obtained the required delay with large channel lengths in the second stage. This means that the bulk of the delay is caused by the third stage gate capacitances.

Bottom Line: It provides differences in the dynamic response so that the direct-path current in the next stage is reduced.The energy (charge) per delay is reduced up to 40%.The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

View Article: PubMed Central - PubMed

Affiliation: Faculty of Electrical Engineering, University of Ljubljana, Tržaška 25, 1000 Ljubljana, Slovenia.

ABSTRACT
A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Show MeSH
Related in: MedlinePlus