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Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

Chin FT, Lin YH, You HC, Yang WL, Lin LM, Hsiao YP, Ko CM, Chao TS - Nanoscale Res Lett (2014)

Bottom Line: As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased.Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time.Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

View Article: PubMed Central - HTML - PubMed

Affiliation: Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, No. 100 Wenhwa Rd., Seatwen, Taichung 40724, Taiwan.

ABSTRACT
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

No MeSH data available.


Date retention characteristics of control and CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM at 85°C testing. The inset of the figure showing ohmic conduction in the control sample after HRS degenerate to LRS.
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Figure 6: Date retention characteristics of control and CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM at 85°C testing. The inset of the figure showing ohmic conduction in the control sample after HRS degenerate to LRS.

Mentions: Next, the effect of thermal stress on the control and CDT samples was investigated. Figure 6 shows the data retention properties of samples exposed to high temperature (85°C). The DC sweep was first turned on and off, and the CDT samples were measured at 0.1 V readout. The HRS characteristics revealed a shorter data retention time in the control samples than in the CDT-fabricated samples. Subsequent to HRS failure, the control sample could be reset to turn off the HRS, as shown in Figure 6 (inset). Post HRS failure, the fitting results of current conduction mechanism in the control sample is ohmic conduction. This implies that HRS failure occurs by the reconnection of the Cu conductive filaments [8,12]. In HRS under high thermal stress, the Cu residue in the switching layer could diffuse from high to low concentration regions and reconnect to the Cu conductive filaments induced by readout voltage stress. The CDT samples also exhibited more stable HRS characteristics than the control sample. This result is attributable to the low forming operation voltage of the CDT samples, which limits the concentration of Cu atoms entering the SiO2 switching layer. Consequently, the probability that Cu conductive filaments reconnect remains small. In addition, the LRS property is reportedly related to the size of the Cu conductive filaments [15]. Thin Cu conductive filaments are easily ruptured by baking at high temperatures because the metal ions readily migrate [15]. However, the LRS property of samples fabricated at short CDT processing times was negligibly degraded under high-temperature testing. This demonstrates the strong reliability of the CDT samples and highlights their potential in nonvolatile resistive switching memory applications. The endurance switching cycle characteristics of the CDT samples are shown in Figure 7. For all samples, these tests were performed using DC sweep cycles and a readout voltage of 0.1 V. The endurance switching cycle times of the CDT samples increased with decreasing CDT processing time. Failure of the endurance switching cycle is attributable to the Joule heating effect [16]. Repeated application of set/reset ultimately destroys the switching layer gap between the electrode and the Cu conductive filaments [16]. The increased endurance period of the switching cycle at shorter CDT processing times may be ascribed to the thin Cu conductive filaments formed in the switching layer. Because the operating current and reset voltage were reduced in the thin filaments, the joule heating effect was lowered and the switching layer gap was more likely preserved. Therefore, the Cu CDT process can achieve Cu/insulator-stacked devices with highly efficient and reliable switching characteristics for use in high-performance ECM-type ReRAMs.


Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

Chin FT, Lin YH, You HC, Yang WL, Lin LM, Hsiao YP, Ko CM, Chao TS - Nanoscale Res Lett (2014)

Date retention characteristics of control and CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM at 85°C testing. The inset of the figure showing ohmic conduction in the control sample after HRS degenerate to LRS.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4214826&req=5

Figure 6: Date retention characteristics of control and CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM at 85°C testing. The inset of the figure showing ohmic conduction in the control sample after HRS degenerate to LRS.
Mentions: Next, the effect of thermal stress on the control and CDT samples was investigated. Figure 6 shows the data retention properties of samples exposed to high temperature (85°C). The DC sweep was first turned on and off, and the CDT samples were measured at 0.1 V readout. The HRS characteristics revealed a shorter data retention time in the control samples than in the CDT-fabricated samples. Subsequent to HRS failure, the control sample could be reset to turn off the HRS, as shown in Figure 6 (inset). Post HRS failure, the fitting results of current conduction mechanism in the control sample is ohmic conduction. This implies that HRS failure occurs by the reconnection of the Cu conductive filaments [8,12]. In HRS under high thermal stress, the Cu residue in the switching layer could diffuse from high to low concentration regions and reconnect to the Cu conductive filaments induced by readout voltage stress. The CDT samples also exhibited more stable HRS characteristics than the control sample. This result is attributable to the low forming operation voltage of the CDT samples, which limits the concentration of Cu atoms entering the SiO2 switching layer. Consequently, the probability that Cu conductive filaments reconnect remains small. In addition, the LRS property is reportedly related to the size of the Cu conductive filaments [15]. Thin Cu conductive filaments are easily ruptured by baking at high temperatures because the metal ions readily migrate [15]. However, the LRS property of samples fabricated at short CDT processing times was negligibly degraded under high-temperature testing. This demonstrates the strong reliability of the CDT samples and highlights their potential in nonvolatile resistive switching memory applications. The endurance switching cycle characteristics of the CDT samples are shown in Figure 7. For all samples, these tests were performed using DC sweep cycles and a readout voltage of 0.1 V. The endurance switching cycle times of the CDT samples increased with decreasing CDT processing time. Failure of the endurance switching cycle is attributable to the Joule heating effect [16]. Repeated application of set/reset ultimately destroys the switching layer gap between the electrode and the Cu conductive filaments [16]. The increased endurance period of the switching cycle at shorter CDT processing times may be ascribed to the thin Cu conductive filaments formed in the switching layer. Because the operating current and reset voltage were reduced in the thin filaments, the joule heating effect was lowered and the switching layer gap was more likely preserved. Therefore, the Cu CDT process can achieve Cu/insulator-stacked devices with highly efficient and reliable switching characteristics for use in high-performance ECM-type ReRAMs.

Bottom Line: As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased.Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time.Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

View Article: PubMed Central - HTML - PubMed

Affiliation: Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, No. 100 Wenhwa Rd., Seatwen, Taichung 40724, Taiwan.

ABSTRACT
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

No MeSH data available.