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Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

Chin FT, Lin YH, You HC, Yang WL, Lin LM, Hsiao YP, Ko CM, Chao TS - Nanoscale Res Lett (2014)

Bottom Line: As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased.Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time.Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

View Article: PubMed Central - HTML - PubMed

Affiliation: Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, No. 100 Wenhwa Rd., Seatwen, Taichung 40724, Taiwan.

ABSTRACT
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

No MeSH data available.


Typical bipolar I-V resistive switching characteristics of (a) control and (b) CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM.
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Figure 4: Typical bipolar I-V resistive switching characteristics of (a) control and (b) CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM.

Mentions: Figure 4 shows the typical bipolar I-V resistive switching characteristics of control sample and CDT samples. In the fresh devices, a so-called 'forming process' in which the Cu electrode is subjected to a large positive voltage bias was required for generating resistive switching behavior. The initial high resistance state (HRS) of the devices was then switched to a low resistance state (LRS). Next, the switching characteristics of the devices were repeatedly executed by a DC sweep voltage that cyclically turned the LRS on (set process) and the HRS off (reset process) by applying positive and negative voltage biases, respectively. When applying the positive voltage bias in the forming and set processes, the current was restricted to 100 μA to prevent device hard-breakdown. The voltages of the forming, set, and reset operations were found to be smaller in the CDT-fabricated samples than in the control samples. Because both control and CDT samples are ECM-type ReRAMs, their resistive switching mechanisms are expected to arise from the formation and rupture of Cu conductive filaments. In the CDT samples, the roughness interface appending effect imposed by the CDT processing could enhance the local electric field. Besides, the CDT-fabricated Cu forms different Cu structure (loose structure). The different Cu structure could also be oxidized easily and result in fast drifting into SiO2[12]. Based on these reasons, the consequent rapid dissolution of Cu ions would hasten the formation and rupture of Cu conductive filaments. Thus, the CDT samples obtained lower operation voltages than the control sample. In addition, the forming and set operation voltages of the CDT-fabricated samples decreased with increasing CDT processing time. This result is attributed to the reduction of SiO2 thickness, since each CDT-fabricated sample shows similar electric field for forming and set operation. By contrast, the reset operation voltage and the on-state current (LRS) of the CDT samples decreased as the CDT processing time decreased. The reduced on-state current was implied by the altered thickness of the Cu conductive filaments [12]. Thin Cu conductive filaments would lower the on-state current, and therefore the reset operation voltage, in CDT samples fabricated over short processing times.


Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

Chin FT, Lin YH, You HC, Yang WL, Lin LM, Hsiao YP, Ko CM, Chao TS - Nanoscale Res Lett (2014)

Typical bipolar I-V resistive switching characteristics of (a) control and (b) CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4214826&req=5

Figure 4: Typical bipolar I-V resistive switching characteristics of (a) control and (b) CDT-fabricated Cu/SiO2-stacked (CDT sample) ReRAM.
Mentions: Figure 4 shows the typical bipolar I-V resistive switching characteristics of control sample and CDT samples. In the fresh devices, a so-called 'forming process' in which the Cu electrode is subjected to a large positive voltage bias was required for generating resistive switching behavior. The initial high resistance state (HRS) of the devices was then switched to a low resistance state (LRS). Next, the switching characteristics of the devices were repeatedly executed by a DC sweep voltage that cyclically turned the LRS on (set process) and the HRS off (reset process) by applying positive and negative voltage biases, respectively. When applying the positive voltage bias in the forming and set processes, the current was restricted to 100 μA to prevent device hard-breakdown. The voltages of the forming, set, and reset operations were found to be smaller in the CDT-fabricated samples than in the control samples. Because both control and CDT samples are ECM-type ReRAMs, their resistive switching mechanisms are expected to arise from the formation and rupture of Cu conductive filaments. In the CDT samples, the roughness interface appending effect imposed by the CDT processing could enhance the local electric field. Besides, the CDT-fabricated Cu forms different Cu structure (loose structure). The different Cu structure could also be oxidized easily and result in fast drifting into SiO2[12]. Based on these reasons, the consequent rapid dissolution of Cu ions would hasten the formation and rupture of Cu conductive filaments. Thus, the CDT samples obtained lower operation voltages than the control sample. In addition, the forming and set operation voltages of the CDT-fabricated samples decreased with increasing CDT processing time. This result is attributed to the reduction of SiO2 thickness, since each CDT-fabricated sample shows similar electric field for forming and set operation. By contrast, the reset operation voltage and the on-state current (LRS) of the CDT samples decreased as the CDT processing time decreased. The reduced on-state current was implied by the altered thickness of the Cu conductive filaments [12]. Thin Cu conductive filaments would lower the on-state current, and therefore the reset operation voltage, in CDT samples fabricated over short processing times.

Bottom Line: As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased.Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time.Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

View Article: PubMed Central - HTML - PubMed

Affiliation: Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, No. 100 Wenhwa Rd., Seatwen, Taichung 40724, Taiwan.

ABSTRACT
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

No MeSH data available.