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Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

Chin FT, Lin YH, You HC, Yang WL, Lin LM, Hsiao YP, Ko CM, Chao TS - Nanoscale Res Lett (2014)

Bottom Line: As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased.Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time.Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

View Article: PubMed Central - HTML - PubMed

Affiliation: Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, No. 100 Wenhwa Rd., Seatwen, Taichung 40724, Taiwan.

ABSTRACT
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

No MeSH data available.


AFM image to analyze the surface roughness of SiO2. (a) Control, (b) CDT 60, (c) CDT 65, and (d) CDT 70 s samples.
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Figure 3: AFM image to analyze the surface roughness of SiO2. (a) Control, (b) CDT 60, (c) CDT 65, and (d) CDT 70 s samples.

Mentions: Figure 2 shows scanning electron microscopy (SEM) images of the samples prepared by Cu CDT for 60 and 70 s. The initial SEM testing sample was an Al (100 nm)/PE-TEOS SiO2 (500 nm)/Si-sub structure. After Cu CDT processing, the Al metal film was completely displaced by Cu. The average thickness of the Cu in the 60 and 70-s samples was approximately 198 and 207 nm, respectively, and the thickness of the SiO2 film was reduced by the longer processing time (decreasing ca. 8 nm relative to the shorter time). During the longer period, fluoride ions could react with the SiO2, releasing extra electrons that promoted the reduction of Cu2+ to Cu atoms. For this reason, the Cu metal film was thicker in the 70-s sample than in the 60-s sample. In addition, the attack of F− ions during the longer CDT process roughened the Cu–SiO2 interface. Atomic force microscopy confirmed that the SiO2 surface roughness increased with increasing CDT processing time (Figure 3). We observe the surface roughness of SiO2 film for CDT process by AFM system. For the control sample, we directly scanned the surface of fresh PECVD SiO2 film. As a comparison, the CDT samples were fabricated by the Cu CDT process, and then removed the Cu metal film to observe the revealed SiO2. The results of surface roughness for the SiO2 film were 0.3, 0.968, 1.56 and 1.986 nm for the control, CDT 60, CDT 65, and CDT 70 s, respectively, as shown in Figure 3. The Cu metal in samples fabricated by Cu CDT was removed by wet etching methods, revealing that the shape of the interface could be controlled by CDT.


Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application.

Chin FT, Lin YH, You HC, Yang WL, Lin LM, Hsiao YP, Ko CM, Chao TS - Nanoscale Res Lett (2014)

AFM image to analyze the surface roughness of SiO2. (a) Control, (b) CDT 60, (c) CDT 65, and (d) CDT 70 s samples.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4214826&req=5

Figure 3: AFM image to analyze the surface roughness of SiO2. (a) Control, (b) CDT 60, (c) CDT 65, and (d) CDT 70 s samples.
Mentions: Figure 2 shows scanning electron microscopy (SEM) images of the samples prepared by Cu CDT for 60 and 70 s. The initial SEM testing sample was an Al (100 nm)/PE-TEOS SiO2 (500 nm)/Si-sub structure. After Cu CDT processing, the Al metal film was completely displaced by Cu. The average thickness of the Cu in the 60 and 70-s samples was approximately 198 and 207 nm, respectively, and the thickness of the SiO2 film was reduced by the longer processing time (decreasing ca. 8 nm relative to the shorter time). During the longer period, fluoride ions could react with the SiO2, releasing extra electrons that promoted the reduction of Cu2+ to Cu atoms. For this reason, the Cu metal film was thicker in the 70-s sample than in the 60-s sample. In addition, the attack of F− ions during the longer CDT process roughened the Cu–SiO2 interface. Atomic force microscopy confirmed that the SiO2 surface roughness increased with increasing CDT processing time (Figure 3). We observe the surface roughness of SiO2 film for CDT process by AFM system. For the control sample, we directly scanned the surface of fresh PECVD SiO2 film. As a comparison, the CDT samples were fabricated by the Cu CDT process, and then removed the Cu metal film to observe the revealed SiO2. The results of surface roughness for the SiO2 film were 0.3, 0.968, 1.56 and 1.986 nm for the control, CDT 60, CDT 65, and CDT 70 s, respectively, as shown in Figure 3. The Cu metal in samples fabricated by Cu CDT was removed by wet etching methods, revealing that the shape of the interface could be controlled by CDT.

Bottom Line: As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased.Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time.Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

View Article: PubMed Central - HTML - PubMed

Affiliation: Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, No. 100 Wenhwa Rd., Seatwen, Taichung 40724, Taiwan.

ABSTRACT
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

No MeSH data available.