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Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices.

Logoteta D, Fiori G, Iannaccone G - Sci Rep (2014)

Bottom Line: Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism.We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits.On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

View Article: PubMed Central - PubMed

Affiliation: Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Caruso 16, 56122 Pisa, Italy.

ABSTRACT
We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

No MeSH data available.


(a) LHFET transfer characteristics for EOT = 1 nm and different values of tB. (b), (c) Static and dynamic figures of merit extracted from the simulation data. Points for tB = 11 nm refer to L = 11 nm (channel symmetrically extended on the drain and source side).
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f6: (a) LHFET transfer characteristics for EOT = 1 nm and different values of tB. (b), (c) Static and dynamic figures of merit extracted from the simulation data. Points for tB = 11 nm refer to L = 11 nm (channel symmetrically extended on the drain and source side).

Mentions: We consider a LHFET with a p-type channel. The channel length is L = 10 nm and we consider a top and bottom gate aligned to the channel (see Figure 1 (c)), unless otherwise stated. The length of the p-doped source and drain extensions is set to 10 nm. The barrier region consists of a transversal strip of hBC2N, that we model using the tight-binding parameters proposed in Ref. 23. In Figure 6 (a) we report the transfer characteristics corresponding to different choices of the length tB of the barrier region. The curves look almost superimposed for VGS < −0.5 V, while, for voltages closer to zero, the decrease in tB entails a larger tunneling current component and, thus, an increase in the minimum of the current. SSmin settles to the almost ideal value of ≈64 mV/dec for tB > 7 nm, gradually increasing for lower barrier thickness. Correspondingly, the Ion/Ioff ratio rapidly decreases for tB < 4.5 nm, while it shows slower variations for higher tB (Figure 6 (b)). When tB is increased beyond ≈8 nm, the PDP decreases as a result of the reduction of the fringe capacitances between the gates and the graphene channel: the overall variation in the PDP is however quite small (smaller than 30% for the considered tB values). Apart from fT, that reaches its maximum value for a barrier region slightly shorter than the channel, all the figures of merit are best for tB = L.


Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices.

Logoteta D, Fiori G, Iannaccone G - Sci Rep (2014)

(a) LHFET transfer characteristics for EOT = 1 nm and different values of tB. (b), (c) Static and dynamic figures of merit extracted from the simulation data. Points for tB = 11 nm refer to L = 11 nm (channel symmetrically extended on the drain and source side).
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4202216&req=5

f6: (a) LHFET transfer characteristics for EOT = 1 nm and different values of tB. (b), (c) Static and dynamic figures of merit extracted from the simulation data. Points for tB = 11 nm refer to L = 11 nm (channel symmetrically extended on the drain and source side).
Mentions: We consider a LHFET with a p-type channel. The channel length is L = 10 nm and we consider a top and bottom gate aligned to the channel (see Figure 1 (c)), unless otherwise stated. The length of the p-doped source and drain extensions is set to 10 nm. The barrier region consists of a transversal strip of hBC2N, that we model using the tight-binding parameters proposed in Ref. 23. In Figure 6 (a) we report the transfer characteristics corresponding to different choices of the length tB of the barrier region. The curves look almost superimposed for VGS < −0.5 V, while, for voltages closer to zero, the decrease in tB entails a larger tunneling current component and, thus, an increase in the minimum of the current. SSmin settles to the almost ideal value of ≈64 mV/dec for tB > 7 nm, gradually increasing for lower barrier thickness. Correspondingly, the Ion/Ioff ratio rapidly decreases for tB < 4.5 nm, while it shows slower variations for higher tB (Figure 6 (b)). When tB is increased beyond ≈8 nm, the PDP decreases as a result of the reduction of the fringe capacitances between the gates and the graphene channel: the overall variation in the PDP is however quite small (smaller than 30% for the considered tB values). Apart from fT, that reaches its maximum value for a barrier region slightly shorter than the channel, all the figures of merit are best for tB = L.

Bottom Line: Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism.We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits.On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

View Article: PubMed Central - PubMed

Affiliation: Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Caruso 16, 56122 Pisa, Italy.

ABSTRACT
We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

No MeSH data available.