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A novel sample based quadrature phase shift keying demodulator.

Mohamed Moubark A, Ali SH - ScientificWorldJournal (2014)

Bottom Line: A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform.In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR.Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia.

ABSTRACT
This paper presents a new practical QPSK receiver that uses digitized samples of incoming QPSK analog signal to determine the phase of the QPSK symbol. The proposed technique is more robust to phase noise and consumes up to 89.6% less power for signal detection in demodulation operation. On the contrary, the conventional QPSK demodulation process where it uses coherent detection technique requires the exact incoming signal frequency; thus, any variation in the frequency of the local oscillator or incoming signal will cause phase noise. A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform. In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR. Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

Show MeSH
(a) The QPSK signal, (b) sampling time, (c) output from sampled QPSK signal, and (d) four samples obtained from the sampled QPSK signal.
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fig2: (a) The QPSK signal, (b) sampling time, (c) output from sampled QPSK signal, and (d) four samples obtained from the sampled QPSK signal.

Mentions: The whole demodulation process starts with sampling of the QPSK signal from the signal recovery block by using the sample and hold circuit block. The sample and hold block will convert the continuous QPSK signal, s(t), into discrete signal, S[n], as given by(2)S[n]=s(t)Vr×2y,where n is the number of samples and y is the quantization level. The maximum range of the ADC voltage is ±Vr centered on the reference voltage 0 v. The chosen transmitted carrier frequency was 5 MHz because it is a frequently used bandwidth in wireless systems [9]. Therefore the sampling clock frequency used in sample and hold block was set to 8 times the incoming frequency which is 40 MHz. The sampling clock is set by using pulse generator where the period of the pulse can be programmed. A group, ak{  }, of 8 samples, S[n], are produced for every phase of a QPSK symbol as given by(3)ak{  }=S[n], k=1⋯∞,  n=1~8.Continuously, from the odd samples, S[2m + 1] of ak{  }, a decision is made and sorted according to their polarities, bk{  }, as given by(4)bl{  }={1,  S[2m+1]  >0−1,S[2m+1]  <0m=0,1,2,3, m∈n, l=1⋯∞.The sign block is used after the sampling process to rearrange the sampled data according to the polarity. Figure 2 shows in detail the sampling and grouping process.


A novel sample based quadrature phase shift keying demodulator.

Mohamed Moubark A, Ali SH - ScientificWorldJournal (2014)

(a) The QPSK signal, (b) sampling time, (c) output from sampled QPSK signal, and (d) four samples obtained from the sampled QPSK signal.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4150515&req=5

fig2: (a) The QPSK signal, (b) sampling time, (c) output from sampled QPSK signal, and (d) four samples obtained from the sampled QPSK signal.
Mentions: The whole demodulation process starts with sampling of the QPSK signal from the signal recovery block by using the sample and hold circuit block. The sample and hold block will convert the continuous QPSK signal, s(t), into discrete signal, S[n], as given by(2)S[n]=s(t)Vr×2y,where n is the number of samples and y is the quantization level. The maximum range of the ADC voltage is ±Vr centered on the reference voltage 0 v. The chosen transmitted carrier frequency was 5 MHz because it is a frequently used bandwidth in wireless systems [9]. Therefore the sampling clock frequency used in sample and hold block was set to 8 times the incoming frequency which is 40 MHz. The sampling clock is set by using pulse generator where the period of the pulse can be programmed. A group, ak{  }, of 8 samples, S[n], are produced for every phase of a QPSK symbol as given by(3)ak{  }=S[n], k=1⋯∞,  n=1~8.Continuously, from the odd samples, S[2m + 1] of ak{  }, a decision is made and sorted according to their polarities, bk{  }, as given by(4)bl{  }={1,  S[2m+1]  >0−1,S[2m+1]  <0m=0,1,2,3, m∈n, l=1⋯∞.The sign block is used after the sampling process to rearrange the sampled data according to the polarity. Figure 2 shows in detail the sampling and grouping process.

Bottom Line: A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform.In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR.Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia.

ABSTRACT
This paper presents a new practical QPSK receiver that uses digitized samples of incoming QPSK analog signal to determine the phase of the QPSK symbol. The proposed technique is more robust to phase noise and consumes up to 89.6% less power for signal detection in demodulation operation. On the contrary, the conventional QPSK demodulation process where it uses coherent detection technique requires the exact incoming signal frequency; thus, any variation in the frequency of the local oscillator or incoming signal will cause phase noise. A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform. In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR. Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

Show MeSH