Limits...
A novel sample based quadrature phase shift keying demodulator.

Mohamed Moubark A, Ali SH - ScientificWorldJournal (2014)

Bottom Line: A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform.In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR.Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia.

ABSTRACT
This paper presents a new practical QPSK receiver that uses digitized samples of incoming QPSK analog signal to determine the phase of the QPSK symbol. The proposed technique is more robust to phase noise and consumes up to 89.6% less power for signal detection in demodulation operation. On the contrary, the conventional QPSK demodulation process where it uses coherent detection technique requires the exact incoming signal frequency; thus, any variation in the frequency of the local oscillator or incoming signal will cause phase noise. A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform. In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR. Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

Show MeSH
Block diagram for the proposed 8S-QPSK demodulator.
© Copyright Policy - open-access
Related In: Results  -  Collection


getmorefigures.php?uid=PMC4150515&req=5

fig1: Block diagram for the proposed 8S-QPSK demodulator.

Mentions: The proposed QPSK demodulator uses polarity difference from digitized QPSK signal for the demodulation process and is given a new code name 8S-QPSK. Figure 1 shows the complete block diagram for the proposed design where it consists of analog to digital converter (ADC), first in first out (FIFO), lookup table (LUT), and comparators.


A novel sample based quadrature phase shift keying demodulator.

Mohamed Moubark A, Ali SH - ScientificWorldJournal (2014)

Block diagram for the proposed 8S-QPSK demodulator.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4150515&req=5

fig1: Block diagram for the proposed 8S-QPSK demodulator.
Mentions: The proposed QPSK demodulator uses polarity difference from digitized QPSK signal for the demodulation process and is given a new code name 8S-QPSK. Figure 1 shows the complete block diagram for the proposed design where it consists of analog to digital converter (ADC), first in first out (FIFO), lookup table (LUT), and comparators.

Bottom Line: A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform.In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR.Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia.

ABSTRACT
This paper presents a new practical QPSK receiver that uses digitized samples of incoming QPSK analog signal to determine the phase of the QPSK symbol. The proposed technique is more robust to phase noise and consumes up to 89.6% less power for signal detection in demodulation operation. On the contrary, the conventional QPSK demodulation process where it uses coherent detection technique requires the exact incoming signal frequency; thus, any variation in the frequency of the local oscillator or incoming signal will cause phase noise. A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform. In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10(-6), whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR. Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

Show MeSH