Limits...
Ultra-low-voltage CMOS-based current bleeding mixer with high LO-RF isolation.

Tan GH, Sidek RM, Ramiah H, Chong WK, Lioe de X - ScientificWorldJournal (2014)

Bottom Line: This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application.The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB.The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm(2).

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical and Electronic Engineering, Universiti Putra Malaysia, 43400 Serdang, Malaysia ; Department of Electrical and Electronic Engineering, Segi University, 47810 Petaling Jaya, Selangor, Malaysia.

ABSTRACT
This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm(2).

Show MeSH

Related in: MedlinePlus

IIP3 of the proposed mixer.
© Copyright Policy - open-access
Related In: Results  -  Collection


getmorefigures.php?uid=PMC4150493&req=5

fig5: IIP3 of the proposed mixer.

Mentions: The proposed mixer is implemented on a 0.13 μm standard CMOS technology. The mixer consumes only 1.27 mA of DC current from 0.45 V of supply voltage. The LO-RF isolation in dB is given as [10](5)PIsolation(dBm)=Pflo(LO)(dBm)−Pflo(RF)(dbm),where PIsolation is the isolation between LO and RF port due to the leakage component from LO port, Pflo(LO) is the injected LO power at LO port, and Pflo(RF) is the observed LO power coupled to the RF port. The LO-RF isolation has been measured at a difference discrete LO power as described in Figure 3. It can be observed that from the frequency of 2 GHz to 5 GHz, the isolation achieved is more than 55 dB and at 2.4 GHz, the LO-RF isolation is measured at 60 dB. The isolation technique adapted in this circuit has improved the LO-RF shielding significantly while operating at ultra-Low supply voltage down to 0.45 V. Figure 4 shows the results for LO-IF isolation which measures more than 64 dB at 2.4 GHz. Two-tone test with an input frequency of 2.443 GHz and 2.442 GHz is applied to the RF port with the corresponding LO frequency of 2.439 GHz to quantify the linearity of the mixer. The conversion gain of the proposed mixer is observed to be 7.5 dB with an IIP3 of 1 dBm as shown in Figure 5. Inductors  Ld1 and Ld2 in the proposed mixer of Figure 2 not only function as the DC current source but concurrently resonate out the parasitic capacitance at nodes X1 and X2 to improve the IIP3. The noise figure (NF) is observed to be around 18 dB as illustrated in Figure 6. Table 1 summarizes the design parameters for the proposed mixer and the performance comparison of the proposed architecture respective to other reported works is given in Table 2. The designed mixer has the highest LO-RF isolation and among the lowest in DC power consumption. The measured conversion gain and linearity, IIP3, of the mixer is 7.5 dB and 1 dBm, respectively. The dynamic performance of the architecture is evaluated adapting a figure of merit (FOM) expression, which is highlighted in the following equation, given as [11]:(6)FOM=10log⁡(10G/20·10(IIP3−10)/2010NF/10·P),where G is the conversion gain in dB, IIP3 is the third order linearity in dBm, NF is the noise figure in dB, and P is the power in mW. In reasoning out the performance comparison respective to other reported recent work, the proposed architecture exhibits the highest FOM of 16.67 while relating to power dissipation well below 1 mW. In the loop of recent reported work, the proposed architecture process to be the lowest in power consumption. The photomicrograph of the chip is illustrated in Figure 7, with a corresponding chip area of 0.97 × 0.88 mm2.


Ultra-low-voltage CMOS-based current bleeding mixer with high LO-RF isolation.

Tan GH, Sidek RM, Ramiah H, Chong WK, Lioe de X - ScientificWorldJournal (2014)

IIP3 of the proposed mixer.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4150493&req=5

fig5: IIP3 of the proposed mixer.
Mentions: The proposed mixer is implemented on a 0.13 μm standard CMOS technology. The mixer consumes only 1.27 mA of DC current from 0.45 V of supply voltage. The LO-RF isolation in dB is given as [10](5)PIsolation(dBm)=Pflo(LO)(dBm)−Pflo(RF)(dbm),where PIsolation is the isolation between LO and RF port due to the leakage component from LO port, Pflo(LO) is the injected LO power at LO port, and Pflo(RF) is the observed LO power coupled to the RF port. The LO-RF isolation has been measured at a difference discrete LO power as described in Figure 3. It can be observed that from the frequency of 2 GHz to 5 GHz, the isolation achieved is more than 55 dB and at 2.4 GHz, the LO-RF isolation is measured at 60 dB. The isolation technique adapted in this circuit has improved the LO-RF shielding significantly while operating at ultra-Low supply voltage down to 0.45 V. Figure 4 shows the results for LO-IF isolation which measures more than 64 dB at 2.4 GHz. Two-tone test with an input frequency of 2.443 GHz and 2.442 GHz is applied to the RF port with the corresponding LO frequency of 2.439 GHz to quantify the linearity of the mixer. The conversion gain of the proposed mixer is observed to be 7.5 dB with an IIP3 of 1 dBm as shown in Figure 5. Inductors  Ld1 and Ld2 in the proposed mixer of Figure 2 not only function as the DC current source but concurrently resonate out the parasitic capacitance at nodes X1 and X2 to improve the IIP3. The noise figure (NF) is observed to be around 18 dB as illustrated in Figure 6. Table 1 summarizes the design parameters for the proposed mixer and the performance comparison of the proposed architecture respective to other reported works is given in Table 2. The designed mixer has the highest LO-RF isolation and among the lowest in DC power consumption. The measured conversion gain and linearity, IIP3, of the mixer is 7.5 dB and 1 dBm, respectively. The dynamic performance of the architecture is evaluated adapting a figure of merit (FOM) expression, which is highlighted in the following equation, given as [11]:(6)FOM=10log⁡(10G/20·10(IIP3−10)/2010NF/10·P),where G is the conversion gain in dB, IIP3 is the third order linearity in dBm, NF is the noise figure in dB, and P is the power in mW. In reasoning out the performance comparison respective to other reported recent work, the proposed architecture exhibits the highest FOM of 16.67 while relating to power dissipation well below 1 mW. In the loop of recent reported work, the proposed architecture process to be the lowest in power consumption. The photomicrograph of the chip is illustrated in Figure 7, with a corresponding chip area of 0.97 × 0.88 mm2.

Bottom Line: This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application.The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB.The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm(2).

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical and Electronic Engineering, Universiti Putra Malaysia, 43400 Serdang, Malaysia ; Department of Electrical and Electronic Engineering, Segi University, 47810 Petaling Jaya, Selangor, Malaysia.

ABSTRACT
This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm(2).

Show MeSH
Related in: MedlinePlus