Limits...
Novel synaptic memory device for neuromorphic computing.

Mandal S, El-Amin A, Alexander K, Rajendran B, Jha R - Sci Rep (2014)

Bottom Line: The devices are based on Mn doped HfO₂ material.The model was then utilized to show the application of these devices in speech recognition.A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >10(6) times reduction in the power consumption per learning cycle.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical Engineering and Computer Science, University of Toledo, University of Toledo, OH 43606, USA.

ABSTRACT
This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO₂ material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >10(6) times reduction in the power consumption per learning cycle.

Show MeSH
Dielectric relaxation.(a) relaxation after positive voltage stressing. 2.5 V/100 ms pulse was used for the stressing and the current was measured once the stress was removed. The conductance saturates after 1000 s. (b) relaxation after −2 V/100 ms pulse was applied to a positively stressed device. Saturation of conductance is evident here too.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
getmorefigures.php?uid=PMC4061545&req=5

f4: Dielectric relaxation.(a) relaxation after positive voltage stressing. 2.5 V/100 ms pulse was used for the stressing and the current was measured once the stress was removed. The conductance saturates after 1000 s. (b) relaxation after −2 V/100 ms pulse was applied to a positively stressed device. Saturation of conductance is evident here too.

Mentions: Once the stress is removed from the device, its conductance tends to decay. Such a transient decay of conductance under low bias is usually attributed to dielectric relaxation in high k-dielectrics. This process can be modelled using the Curie-von Schweidler (CS) equation for relaxation18. Figure 4(a) shows the relaxation of conductance after removal of the positive CVS. Based on the fit using CS equation, the time to reach the initial un-excited conductance was estimated to be 3.3 months. However, the device conductance already seems to be saturating towards the end of 1000 s, which would suggest that the conductance is retained. Similar fitting was done for relaxation after a negative pulse was applied to the device. The fitting is given in figure 4(b).


Novel synaptic memory device for neuromorphic computing.

Mandal S, El-Amin A, Alexander K, Rajendran B, Jha R - Sci Rep (2014)

Dielectric relaxation.(a) relaxation after positive voltage stressing. 2.5 V/100 ms pulse was used for the stressing and the current was measured once the stress was removed. The conductance saturates after 1000 s. (b) relaxation after −2 V/100 ms pulse was applied to a positively stressed device. Saturation of conductance is evident here too.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC4061545&req=5

f4: Dielectric relaxation.(a) relaxation after positive voltage stressing. 2.5 V/100 ms pulse was used for the stressing and the current was measured once the stress was removed. The conductance saturates after 1000 s. (b) relaxation after −2 V/100 ms pulse was applied to a positively stressed device. Saturation of conductance is evident here too.
Mentions: Once the stress is removed from the device, its conductance tends to decay. Such a transient decay of conductance under low bias is usually attributed to dielectric relaxation in high k-dielectrics. This process can be modelled using the Curie-von Schweidler (CS) equation for relaxation18. Figure 4(a) shows the relaxation of conductance after removal of the positive CVS. Based on the fit using CS equation, the time to reach the initial un-excited conductance was estimated to be 3.3 months. However, the device conductance already seems to be saturating towards the end of 1000 s, which would suggest that the conductance is retained. Similar fitting was done for relaxation after a negative pulse was applied to the device. The fitting is given in figure 4(b).

Bottom Line: The devices are based on Mn doped HfO₂ material.The model was then utilized to show the application of these devices in speech recognition.A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >10(6) times reduction in the power consumption per learning cycle.

View Article: PubMed Central - PubMed

Affiliation: Department of Electrical Engineering and Computer Science, University of Toledo, University of Toledo, OH 43606, USA.

ABSTRACT
This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO₂ material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >10(6) times reduction in the power consumption per learning cycle.

Show MeSH