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Hardware implementation of 32-bit high-speed direct digital frequency synthesizer.

Ibrahim SH, Ali SH, Islam MS - ScientificWorldJournal (2014)

Bottom Line: A gated clock technique is proposed to reduce the number of registers in the phase accumulator design.These techniques, compressed the ROM into 368 bits.These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronics, College of Engineering, Diyala University, Baqubah, Diyala 32001, Iraq ; Department of Electrical, Electronics & System Engineering, Faculty of Engineering, Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Malaysia.

ABSTRACT
The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

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The block diagram of the final design of high-speed DDFS.
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fig7: The block diagram of the final design of high-speed DDFS.

Mentions: The final design of the high-speed DDFS, which consists of parallel pipelining PA and compressed ROM LUT by using the wave symmetry technique, is shown in Figure 7.


Hardware implementation of 32-bit high-speed direct digital frequency synthesizer.

Ibrahim SH, Ali SH, Islam MS - ScientificWorldJournal (2014)

The block diagram of the final design of high-speed DDFS.
© Copyright Policy - open-access
Related In: Results  -  Collection

Show All Figures
getmorefigures.php?uid=PMC4060586&req=5

fig7: The block diagram of the final design of high-speed DDFS.
Mentions: The final design of the high-speed DDFS, which consists of parallel pipelining PA and compressed ROM LUT by using the wave symmetry technique, is shown in Figure 7.

Bottom Line: A gated clock technique is proposed to reduce the number of registers in the phase accumulator design.These techniques, compressed the ROM into 368 bits.These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

View Article: PubMed Central - PubMed

Affiliation: Department of Electronics, College of Engineering, Diyala University, Baqubah, Diyala 32001, Iraq ; Department of Electrical, Electronics & System Engineering, Faculty of Engineering, Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Malaysia.

ABSTRACT
The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

Show MeSH
Related in: MedlinePlus