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Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory.

Yeh MS, Wu YC, Hung MF, Liu KC, Jhan YR, Chen LC, Chang CY - Nanoscale Res Lett (2013)

Bottom Line: This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs).Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency.This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

View Article: PubMed Central - HTML - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2 Kuang Fu Road, Hsinchu, 30013, Taiwan. ycwu@ess.nthu.edu.tw.

ABSTRACT
This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

No MeSH data available.


Programming and erasing characteristics of the EEPROM cell with devices. The P/E speed of BBHE operation is compared with that of FN operation.
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Figure 3: Programming and erasing characteristics of the EEPROM cell with devices. The P/E speed of BBHE operation is compared with that of FN operation.

Mentions: Figure 3 compares the P/E speed of the BBHE operation with that of the FN operation. The device was programmed by FN injection at Vgs = 17 V and by BBHE injection at Vgs = 7 V with Vds = −10 V. The BBHE operation exhibits higher programming speed than the FN operation.


Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory.

Yeh MS, Wu YC, Hung MF, Liu KC, Jhan YR, Chen LC, Chang CY - Nanoscale Res Lett (2013)

Programming and erasing characteristics of the EEPROM cell with devices. The P/E speed of BBHE operation is compared with that of FN operation.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3733706&req=5

Figure 3: Programming and erasing characteristics of the EEPROM cell with devices. The P/E speed of BBHE operation is compared with that of FN operation.
Mentions: Figure 3 compares the P/E speed of the BBHE operation with that of the FN operation. The device was programmed by FN injection at Vgs = 17 V and by BBHE injection at Vgs = 7 V with Vds = −10 V. The BBHE operation exhibits higher programming speed than the FN operation.

Bottom Line: This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs).Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency.This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

View Article: PubMed Central - HTML - PubMed

Affiliation: Department of Engineering and System Science, National Tsing Hua University, 101, Section 2 Kuang Fu Road, Hsinchu, 30013, Taiwan. ycwu@ess.nthu.edu.tw.

ABSTRACT
This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

No MeSH data available.