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Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

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Power Distribution at Points C1, C2, and C3.
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f8-sensors-12-10067: Power Distribution at Points C1, C2, and C3.

Mentions: The proposed scaling of the sensor supplies substantially affects the power distribution (Figure 8). At point C1, the digital part almost does not consume power, thus the majority of it is dissipated within the analog domain. At point C2, which was the traditional operation point used before that presented in this article analysis; most of the power is divided almost equally between the AVDD and the DVDD. The effect of aggressive scaling of the digital supply can be clearly seen at point C3, where approximately ¾ of the overall power is consumed by the AVDD.


Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Power Distribution at Points C1, C2, and C3.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3472816&req=5

f8-sensors-12-10067: Power Distribution at Points C1, C2, and C3.
Mentions: The proposed scaling of the sensor supplies substantially affects the power distribution (Figure 8). At point C1, the digital part almost does not consume power, thus the majority of it is dissipated within the analog domain. At point C2, which was the traditional operation point used before that presented in this article analysis; most of the power is divided almost equally between the AVDD and the DVDD. The effect of aggressive scaling of the digital supply can be clearly seen at point C3, where approximately ¾ of the overall power is consumed by the AVDD.

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Show MeSH
Related in: MedlinePlus