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Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

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f5-sensors-12-10067: Sensor Test Board.

Mentions: The presented 128 × 256 sensor was successfully implemented in a 0.18 μm CIS process. The fabricated chip was mounted on a test board (Figure 5), which powered the chip supplies and controlled the logic functions. Digital outputs of the sensor were scanned to the on-board static memory, while the analog output was fed to the on board pipelined A/D converter. PC software was used to image the captured scene. Various experiments were conducted to test a single pixel and the whole system performance. The final goal of the experiments was to verify the sensor functionality and its power consumption with variable power supplies. The measured results were in full agreement with the theoretical assessments; hence, they proved the feasibility of the proposed supply scaling and other low voltage design techniques implemented in the reported imager.


Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Sensor Test Board.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3472816&req=5

f5-sensors-12-10067: Sensor Test Board.
Mentions: The presented 128 × 256 sensor was successfully implemented in a 0.18 μm CIS process. The fabricated chip was mounted on a test board (Figure 5), which powered the chip supplies and controlled the logic functions. Digital outputs of the sensor were scanned to the on-board static memory, while the analog output was fed to the on board pipelined A/D converter. PC software was used to image the captured scene. Various experiments were conducted to test a single pixel and the whole system performance. The final goal of the experiments was to verify the sensor functionality and its power consumption with variable power supplies. The measured results were in full agreement with the theoretical assessments; hence, they proved the feasibility of the proposed supply scaling and other low voltage design techniques implemented in the reported imager.

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Show MeSH
Related in: MedlinePlus