Limits...
Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Show MeSH

Related in: MedlinePlus

A standard 8T bitcell.
© Copyright Policy
Related In: Results  -  Collection

License
getmorefigures.php?uid=PMC3472816&req=5

f4-sensors-12-10067: A standard 8T bitcell.

Mentions: The general topology of the SRAM we used is the two-port 8-T bit-cell, which decouples the readout from the cell core (Figure 4). The structure employs a standard 6T bitcell core (M1-M6) with an additional pair of transistors (M7-M8) that comprise a readout buffer. Separate word lines (WWL and RWL) and bitlines (WBL, WBLB and RBL) are employed for write and read operations, respectively. In this way, during read operations, the bit-cell data is left undisturbed and therefore, the read margin is equivalent to the hold margin. However, the write margin remains a limitation for this type of cell, due to the rationed contention between the pull-up PMOS devices and the NMOS access devices during the write operations. In addition, for truly random accessible arrays, another situation occurs, known as “half select”, when only some of the bits in a row are written to. This presents a similar situation to a standard single-port read, as the bitlines of non-accessed cells are precharged.


Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

A standard 8T bitcell.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3472816&req=5

f4-sensors-12-10067: A standard 8T bitcell.
Mentions: The general topology of the SRAM we used is the two-port 8-T bit-cell, which decouples the readout from the cell core (Figure 4). The structure employs a standard 6T bitcell core (M1-M6) with an additional pair of transistors (M7-M8) that comprise a readout buffer. Separate word lines (WWL and RWL) and bitlines (WBL, WBLB and RBL) are employed for write and read operations, respectively. In this way, during read operations, the bit-cell data is left undisturbed and therefore, the read margin is equivalent to the hold margin. However, the write margin remains a limitation for this type of cell, due to the rationed contention between the pull-up PMOS devices and the NMOS access devices during the write operations. In addition, for truly random accessible arrays, another situation occurs, known as “half select”, when only some of the bits in a row are written to. This presents a similar situation to a standard single-port read, as the bitlines of non-accessed cells are precharged.

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Show MeSH
Related in: MedlinePlus