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Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

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Schematic of the Logic Processing block.
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f3-sensors-12-10067: Schematic of the Logic Processing block.

Mentions: All the blocks, discussed above, are powered by the analog supply, except for several externally generated bias lines. However, there is one unique block, the Logic Processing (LPR) unit (Figure 3) which relates to the analog power domain, but is powered by both power supplies. In this work we briefly describe its operation, but more detailed information can be found in [6]. The LPR unit is related to the analog domain, since most of its circuits are analog and not digital. However, there are several digital units that were included within the LPR. Incorporating digital blocks beside the analog blocks was necessary, since the LPR communicates with both the APS and the SRAM. The aim of the LPR block is to decide whether a certain pixel has to be reset or not at the current saturation check. The decision of the reset is received by ANDing the comparator Comp output with the result of the previous saturation check retrieved from the SRAM: Mem_rd signal. Please note that this output is in the digital domain. However, in the LPR unit, it takes part in switching of logic gates that are powered by the supply, the value of which equals AVDD, so a step up booster is inevitable. The step up function was implemented using a typical non-inverting amplifier Amp (Figure 3). We chose not to use the conventional level shifter structure, since we wanted to allow the logic to function with a sufficient speed under the widest possible range of DVDD values. The input of the conventional level shifter is composed out of native or high threshold NMOS transistors. Therefore, when the signal at their gate is far below the threshold voltage, they do not operate at all. Even when the input approaches the threshold, NMOS still operate relatively slow. On the other hand, the utilized non-inverting amplifier has input PMOS transistors and therefore can operate at ultra-low input voltages. From the simulations, we concluded that it can successfully elevate voltage signals as low as 0.3 V up to 2.5 V with a delay of couple of nanoseconds. In this way, we could examine the DR extension, when the digital circuits were found deeply in the weak inversion region.


Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Schematic of the Logic Processing block.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3472816&req=5

f3-sensors-12-10067: Schematic of the Logic Processing block.
Mentions: All the blocks, discussed above, are powered by the analog supply, except for several externally generated bias lines. However, there is one unique block, the Logic Processing (LPR) unit (Figure 3) which relates to the analog power domain, but is powered by both power supplies. In this work we briefly describe its operation, but more detailed information can be found in [6]. The LPR unit is related to the analog domain, since most of its circuits are analog and not digital. However, there are several digital units that were included within the LPR. Incorporating digital blocks beside the analog blocks was necessary, since the LPR communicates with both the APS and the SRAM. The aim of the LPR block is to decide whether a certain pixel has to be reset or not at the current saturation check. The decision of the reset is received by ANDing the comparator Comp output with the result of the previous saturation check retrieved from the SRAM: Mem_rd signal. Please note that this output is in the digital domain. However, in the LPR unit, it takes part in switching of logic gates that are powered by the supply, the value of which equals AVDD, so a step up booster is inevitable. The step up function was implemented using a typical non-inverting amplifier Amp (Figure 3). We chose not to use the conventional level shifter structure, since we wanted to allow the logic to function with a sufficient speed under the widest possible range of DVDD values. The input of the conventional level shifter is composed out of native or high threshold NMOS transistors. Therefore, when the signal at their gate is far below the threshold voltage, they do not operate at all. Even when the input approaches the threshold, NMOS still operate relatively slow. On the other hand, the utilized non-inverting amplifier has input PMOS transistors and therefore can operate at ultra-low input voltages. From the simulations, we concluded that it can successfully elevate voltage signals as low as 0.3 V up to 2.5 V with a delay of couple of nanoseconds. In this way, we could examine the DR extension, when the digital circuits were found deeply in the weak inversion region.

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Show MeSH
Related in: MedlinePlus