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Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

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(a) Pixel schematic; (b) Pixel layout.
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f2-sensors-12-10067: (a) Pixel schematic; (b) Pixel layout.

Mentions: The analog power domain contains the pixel array and its periphery. An Active Pixels Sensor (APS) array is composed of 128 × 256 pixels (Figure 1). The photo-detecting element of each pixel is a Pinned Photodiode (PPD, Figure 2(a)). Herein, a photo-generated charge is transferred to integration capacitance C1, through transistor M1, controlled by the Sh_Sw signal. This charge transfer occurs at the selected time points throughout the integration. Since the PPD has a limited charge capacity, it can become flooded with charge before the last is passed on to C1. In such a case, if the charge is not supplied an alternative way, it will spill out uncontrollably from the PPD to the adjacent areas, causing the pixel to bloom. In order to prevent the blooming of the PPD, we included a separate transistor M2, which is controlled by the global signal AB. Thus, the overflowing charge, which cannot be transferred to C1 integration capacitance, is dumped to the AVDD potential (Figure 2(a)). Moreover, by activating AB at the end of the frame, we ensured that the residual charge, which was not transferred to the integration capacitance C1, was drained out, thus preventing the image lag. It is important to note that both AB and Sh_Sw signals are always activated globally. Hence, the charge transfer throughout the array is applied to all the pixels simultaneously. Such simultaneous charge transfers enable the global (snapshot) operation of the presented sensor.


Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

Spivak A, Teman A, Belenky A, Yadid-Pecht O, Fish A - Sensors (Basel) (2012)

(a) Pixel schematic; (b) Pixel layout.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3472816&req=5

f2-sensors-12-10067: (a) Pixel schematic; (b) Pixel layout.
Mentions: The analog power domain contains the pixel array and its periphery. An Active Pixels Sensor (APS) array is composed of 128 × 256 pixels (Figure 1). The photo-detecting element of each pixel is a Pinned Photodiode (PPD, Figure 2(a)). Herein, a photo-generated charge is transferred to integration capacitance C1, through transistor M1, controlled by the Sh_Sw signal. This charge transfer occurs at the selected time points throughout the integration. Since the PPD has a limited charge capacity, it can become flooded with charge before the last is passed on to C1. In such a case, if the charge is not supplied an alternative way, it will spill out uncontrollably from the PPD to the adjacent areas, causing the pixel to bloom. In order to prevent the blooming of the PPD, we included a separate transistor M2, which is controlled by the global signal AB. Thus, the overflowing charge, which cannot be transferred to C1 integration capacitance, is dumped to the AVDD potential (Figure 2(a)). Moreover, by activating AB at the end of the frame, we ensured that the residual charge, which was not transferred to the integration capacitance C1, was drained out, thus preventing the image lag. It is important to note that both AB and Sh_Sw signals are always activated globally. Hence, the charge transfer throughout the array is applied to all the pixels simultaneously. Such simultaneous charge transfers enable the global (snapshot) operation of the presented sensor.

Bottom Line: This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory.The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design.An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

View Article: PubMed Central - PubMed

Affiliation: The VLSI Systems Center, LPCAS, Ben-Gurion University, P.O.B. 653, Be'er-Sheva 84105, Israel. spivakar@bgu.ac.il

ABSTRACT
Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

Show MeSH
Related in: MedlinePlus