Limits...
Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Show MeSH
(a) Photograph of a 3-bit decoder circuit and ferroelectric capacitor memory. Four redundant sub-units were included in this photograph for yield improvement. (b) Input (black dotted line) and output (red line) signals through the printed decoder circuit. The output signal follows the input if the decoder sub-unit is addressed, whereas the output signal is floating when the sub-unit is un-addressed. (c) Bit-line signals read from a 2×2 array of memory capacitors patterned by photolithography. The two lines with different shades of green represent two neighboring bit-lines. Remnant polarization PR is indicated by the black arrow. (d) Same as (c) but the memory capacitors were patterned by gravure printing.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
getmorefigures.php?uid=PMC3420218&req=5

f6: (a) Photograph of a 3-bit decoder circuit and ferroelectric capacitor memory. Four redundant sub-units were included in this photograph for yield improvement. (b) Input (black dotted line) and output (red line) signals through the printed decoder circuit. The output signal follows the input if the decoder sub-unit is addressed, whereas the output signal is floating when the sub-unit is un-addressed. (c) Bit-line signals read from a 2×2 array of memory capacitors patterned by photolithography. The two lines with different shades of green represent two neighboring bit-lines. Remnant polarization PR is indicated by the black arrow. (d) Same as (c) but the memory capacitors were patterned by gravure printing.

Mentions: A photograph of the decoder connected to the memory array is shown in Fig. 6(a). To match the 12-word-line memory array, the decoder was fabricated with twelve sub-units, four of which have redundant addresses. Experimental verification of decoder functionality is demonstrated in Fig. 6(b). With input A held at a constant value, the decoder unit passes the switching signal from input B to output Y only when it is addressed. With any other combination of address signals, the output Y is floating.


Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

(a) Photograph of a 3-bit decoder circuit and ferroelectric capacitor memory. Four redundant sub-units were included in this photograph for yield improvement. (b) Input (black dotted line) and output (red line) signals through the printed decoder circuit. The output signal follows the input if the decoder sub-unit is addressed, whereas the output signal is floating when the sub-unit is un-addressed. (c) Bit-line signals read from a 2×2 array of memory capacitors patterned by photolithography. The two lines with different shades of green represent two neighboring bit-lines. Remnant polarization PR is indicated by the black arrow. (d) Same as (c) but the memory capacitors were patterned by gravure printing.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3420218&req=5

f6: (a) Photograph of a 3-bit decoder circuit and ferroelectric capacitor memory. Four redundant sub-units were included in this photograph for yield improvement. (b) Input (black dotted line) and output (red line) signals through the printed decoder circuit. The output signal follows the input if the decoder sub-unit is addressed, whereas the output signal is floating when the sub-unit is un-addressed. (c) Bit-line signals read from a 2×2 array of memory capacitors patterned by photolithography. The two lines with different shades of green represent two neighboring bit-lines. Remnant polarization PR is indicated by the black arrow. (d) Same as (c) but the memory capacitors were patterned by gravure printing.
Mentions: A photograph of the decoder connected to the memory array is shown in Fig. 6(a). To match the 12-word-line memory array, the decoder was fabricated with twelve sub-units, four of which have redundant addresses. Experimental verification of decoder functionality is demonstrated in Fig. 6(b). With input A held at a constant value, the decoder unit passes the switching signal from input B to output Y only when it is addressed. With any other combination of address signals, the output Y is floating.

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Show MeSH