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Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

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Voltage input to memory word lines and bit lines during (a) the read/reset/write 1 or (b) the write 0 process.
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f5: Voltage input to memory word lines and bit lines during (a) the read/reset/write 1 or (b) the write 0 process.

Mentions: In a memory array, each word line and bit line are connected to multiple cells. To prevent unintentional disturbs during read and write events, the potential across unaddressed cells must be kept below a threshold, nominally one-third of the writing voltage, Vdr. One method to accomplish this is to actively drive addressed and unaddressed word lines and bit lines with the signals shown in Fig. 5. In the read process, all memory cells on the selected word line are read simultaneously by individual charge integrators. The bit lines and unaddressed word lines are held at ground while the addressed word line is driven to Vdr. During reading, all cells connected to the addressed word line are set to 1, the default state. To write a cell to 0, its word line is set to ground and its bit line to Vdr. All unaddressed word lines are held at and all unaddressed bit lines are held at . With these waveforms, the absolute potential across any unaddressed cell is at most and is below disturb threshold. A 2×2 array is the smallest memory that requires the full set of read/write waveforms in Fig. 5. As such, it is the minimum memory size required to demonstrate scalability.


Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

Voltage input to memory word lines and bit lines during (a) the read/reset/write 1 or (b) the write 0 process.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3420218&req=5

f5: Voltage input to memory word lines and bit lines during (a) the read/reset/write 1 or (b) the write 0 process.
Mentions: In a memory array, each word line and bit line are connected to multiple cells. To prevent unintentional disturbs during read and write events, the potential across unaddressed cells must be kept below a threshold, nominally one-third of the writing voltage, Vdr. One method to accomplish this is to actively drive addressed and unaddressed word lines and bit lines with the signals shown in Fig. 5. In the read process, all memory cells on the selected word line are read simultaneously by individual charge integrators. The bit lines and unaddressed word lines are held at ground while the addressed word line is driven to Vdr. During reading, all cells connected to the addressed word line are set to 1, the default state. To write a cell to 0, its word line is set to ground and its bit line to Vdr. All unaddressed word lines are held at and all unaddressed bit lines are held at . With these waveforms, the absolute potential across any unaddressed cell is at most and is below disturb threshold. A 2×2 array is the smallest memory that requires the full set of read/write waveforms in Fig. 5. As such, it is the minimum memory size required to demonstrate scalability.

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Show MeSH