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Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

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Simulation outputs of (a) NAND logic and (b) NAND logic with inverter. (c) Simulation outputs of transmission gates.
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f4: Simulation outputs of (a) NAND logic and (b) NAND logic with inverter. (c) Simulation outputs of transmission gates.

Mentions: From circuit simulations, the fan-out-of-one delay is found to be approximate 0.5 ms for the fastest OTFTs and approximately 0.85 ms for the slowest OTFTs. Figures 4(a) and 4(b) show the timing from a NAND-input signal (s0) edge to the transmission gate control signals using both “FF” (fast-fast) and “SS” (slow-slow) process corners. The “FF” corner switches fully in 1 ms and to VDD/2 in 400 μs. The “SS” corner switches fully in 2.6 ms and to VDD/2 in 2 ms. Figure 4(c) shows simulated waveforms of transmission gate signals. Because of the low on/off ratio of the OTFTs and the shunt conductance of the memory cells, 17.6 V must be applied to the selected transmission gate input to achieve the desired 16 V output in the “SS” process corner. With this same overdrive, the output of a transmission gate in the “FF” corner is 17.2 V; the increased output voltage is acceptable for this memory decoder application.


Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

Simulation outputs of (a) NAND logic and (b) NAND logic with inverter. (c) Simulation outputs of transmission gates.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3420218&req=5

f4: Simulation outputs of (a) NAND logic and (b) NAND logic with inverter. (c) Simulation outputs of transmission gates.
Mentions: From circuit simulations, the fan-out-of-one delay is found to be approximate 0.5 ms for the fastest OTFTs and approximately 0.85 ms for the slowest OTFTs. Figures 4(a) and 4(b) show the timing from a NAND-input signal (s0) edge to the transmission gate control signals using both “FF” (fast-fast) and “SS” (slow-slow) process corners. The “FF” corner switches fully in 1 ms and to VDD/2 in 400 μs. The “SS” corner switches fully in 2.6 ms and to VDD/2 in 2 ms. Figure 4(c) shows simulated waveforms of transmission gate signals. Because of the low on/off ratio of the OTFTs and the shunt conductance of the memory cells, 17.6 V must be applied to the selected transmission gate input to achieve the desired 16 V output in the “SS” process corner. With this same overdrive, the output of a transmission gate in the “FF” corner is 17.2 V; the increased output voltage is acceptable for this memory decoder application.

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Show MeSH
Related in: MedlinePlus