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Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

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(a) Transfer characteristics of printed p- and n-channel OTFTs, with channel length of 2.75 mm and width of 35 μm, in saturation regime Vds = ±20 V and Vgs = ±20 V. The dotted lines represent best-fit models for slow, typical, and fast OTFTs. Histograms of current distribution (b) and on/off ratio (c) were taken from measurements in linear regime Vds = ±5 V and Vgs = ±20 V for lower bound estimation. (d) Normalized current during operation with Vds = ±20 V and Vgs = ±20 V at constant gate bias or at pulsed gate bias of 1 kHz, 50% duty cycle.
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f2: (a) Transfer characteristics of printed p- and n-channel OTFTs, with channel length of 2.75 mm and width of 35 μm, in saturation regime Vds = ±20 V and Vgs = ±20 V. The dotted lines represent best-fit models for slow, typical, and fast OTFTs. Histograms of current distribution (b) and on/off ratio (c) were taken from measurements in linear regime Vds = ±5 V and Vgs = ±20 V for lower bound estimation. (d) Normalized current during operation with Vds = ±20 V and Vgs = ±20 V at constant gate bias or at pulsed gate bias of 1 kHz, 50% duty cycle.

Mentions: The key transistor performance parameters for logic design are the on current and the on/off current ratio. The transfer characteristics of p- and n-channel OTFTs are shown in Fig. 2. In each type of device, for given bias conditions, there is a six-fold device-to-device variation in drain current. This level of variability is comparable to that of photolithographically defined organic transistors10, indicating that printing-specific factors, such as inconsistent source-drain spacing, represent only a minor contribution. The primary sources of the variability are morphology and thickness variations in the semiconductor film, which are observed in both printed and photolithographic processes.


Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

Ng TN, Schwartz DE, Lavery LL, Whiting GL, Russo B, Krusor B, Veres J, Bröms P, Herlogsson L, Alam N, Hagel O, Nilsson J, Karlsson C - Sci Rep (2012)

(a) Transfer characteristics of printed p- and n-channel OTFTs, with channel length of 2.75 mm and width of 35 μm, in saturation regime Vds = ±20 V and Vgs = ±20 V. The dotted lines represent best-fit models for slow, typical, and fast OTFTs. Histograms of current distribution (b) and on/off ratio (c) were taken from measurements in linear regime Vds = ±5 V and Vgs = ±20 V for lower bound estimation. (d) Normalized current during operation with Vds = ±20 V and Vgs = ±20 V at constant gate bias or at pulsed gate bias of 1 kHz, 50% duty cycle.
© Copyright Policy - open-access
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3420218&req=5

f2: (a) Transfer characteristics of printed p- and n-channel OTFTs, with channel length of 2.75 mm and width of 35 μm, in saturation regime Vds = ±20 V and Vgs = ±20 V. The dotted lines represent best-fit models for slow, typical, and fast OTFTs. Histograms of current distribution (b) and on/off ratio (c) were taken from measurements in linear regime Vds = ±5 V and Vgs = ±20 V for lower bound estimation. (d) Normalized current during operation with Vds = ±20 V and Vgs = ±20 V at constant gate bias or at pulsed gate bias of 1 kHz, 50% duty cycle.
Mentions: The key transistor performance parameters for logic design are the on current and the on/off current ratio. The transfer characteristics of p- and n-channel OTFTs are shown in Fig. 2. In each type of device, for given bias conditions, there is a six-fold device-to-device variation in drain current. This level of variability is comparable to that of photolithographically defined organic transistors10, indicating that printing-specific factors, such as inconsistent source-drain spacing, represent only a minor contribution. The primary sources of the variability are morphology and thickness variations in the semiconductor film, which are observed in both printed and photolithographic processes.

Bottom Line: The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics.Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices.We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

View Article: PubMed Central - PubMed

Affiliation: Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304, USA. tnng@parc.com

ABSTRACT
Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Show MeSH