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A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.


Schematics of memristor emulator-based synaptic circuit corresponding to the synaptic structure of Figure 5.
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f6-sensors-12-03587: Schematics of memristor emulator-based synaptic circuit corresponding to the synaptic structure of Figure 5.

Mentions: Figure 6 illustrates the memristor bridge synaptic circuit using four memristor emulators. In this architecture, the input current of the first memristor emulator M1 is replicated by a current mirror and fed to the second memristor emulator M2 to produce its voltage in the memristor emulator. The voltage produced in the second emulator is added to the first emulator with an analog voltage adder. Therefore, the sum of the individual voltage across each serially connected memristor equals to the input voltage.


A voltage mode memristor bridge synaptic circuit with memristor emulators.

Sah MP, Yang C, Kim H, Chua L - Sensors (Basel) (2012)

Schematics of memristor emulator-based synaptic circuit corresponding to the synaptic structure of Figure 5.
© Copyright Policy
Related In: Results  -  Collection

License
Show All Figures
getmorefigures.php?uid=PMC3376599&req=5

f6-sensors-12-03587: Schematics of memristor emulator-based synaptic circuit corresponding to the synaptic structure of Figure 5.
Mentions: Figure 6 illustrates the memristor bridge synaptic circuit using four memristor emulators. In this architecture, the input current of the first memristor emulator M1 is replicated by a current mirror and fed to the second memristor emulator M2 to produce its voltage in the memristor emulator. The voltage produced in the second emulator is added to the first emulator with an analog voltage adder. Therefore, the sum of the individual voltage across each serially connected memristor equals to the input voltage.

Bottom Line: This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits.In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits.The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

View Article: PubMed Central - PubMed

Affiliation: Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea. maheshwarsah@hotmail.com

ABSTRACT
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

No MeSH data available.